Frontiers in Hardware Security and Trust: Theory, design and practice(Materials, Circuits and Devices)

Frontiers in Hardware Security and Trust provides a comprehensive review of emerging security threats and privacy protection issues, and the versatile state-of-the-art hardware-based security countermeasures and applications proposed by the hardware security community. The footprint and power constraints imposed on internet-of-things end-points, smart sensors, mobile and ad hoc network devices make traditional and software based cryptographic solutions that require a general-purpose processor increasingly unfeasible. The fact that security is not the primary functionality of these devices means that only a small portion of their limited processing power and storage is available for security, driving the need for alternative security solutions. Hardware security - including hardware obfuscation, hardware security primitives, side-channel attacks and so on - is therefore becoming an increasingly active research area in both academia and industry. This book discusses the fundamentals of reversible logics, hardware obfuscations, SAT resistant logic obfuscation, and design-for-security. Novel security primitives such as state-of-the-art true random number generators are also explored. Modern micro-architectural attacks enabled with the superscalar microprocessors and its countermeasures are analysed to shed light on how existing architectures can be fortified or made more robust against attack. The introduction of hardware security into cognitive radio networks, 5G networks and machine learning, which are widely considered to be the most promising major contributors to next wave of technological growth, are also discussed. The book serves as an advanced reference for researchers on current hardware security problems, challenges and solutions.

Table of Contents:
Part I: Hardware security threats Chapter 1: IP/IC piracy threats of reversible circuits Chapter 2: Improvements and recent updates of persistent fault analysis on block ciphers Chapter 3: Deployment of EMC techniques in design of IC chips for hardware security Part II: Design for security Chapter 4: Hardware obfuscation for IP protection Chapter 5: Formal verification for SoC security Chapter 6: Silicon-based true random number generators Chapter 7: Micro-architectural attacks and countermeasures on public-key implementations Chapter 8: Mitigating the CACHEKIT attack Chapter 9: Deep learning network security Chapter 10: Security implications of non-digital components Chapter 11: Accelerating homomorphic encryption in hardware: a review Chapter 12: Information leakage from robust codes protecting cryptographic primitives Part III: Physical-layer security Chapter 13: Confidential and energy-efficient cognitive communications by physical-layer security Chapter 14: Physical-layer security for mmWave massive MIMO communications in 5G networks Chapter 15: Security of in-vehicle controller area network: a review and future directions

About the Author :
Chip Hong Chang is a tenured associate professor at the School of Electrical and Electronic Engineering (EEE), Nanyang Technological University, Singapore. He has edited and co-edited five books and published 13 chapters, over 100 international journal papers and more than 180 refereed international conference papers. His research interests are hardware security, residue and unconventional number systems, low-power arithmetic circuits, digital filter design and digital image processing. He is a fellow of the IEEE and the IET. Yuan Cao is a professor at the College of Internet of Things Engineering, Hohai University, China. His research interests include hardware security, silicon physical unclonable function, and analog/mixed-signal VLSI circuits and systems.