Advances in Hardware Design for Security and Trust: (Computer Hardware Security and Correctness)

This book addresses various electronics supply-chain vulnerabilities, attack methods that exploit these vulnerabilities, and design techniques to mitigate the vulnerabilities while defending against the attacks. This book covers the entire spectrum of electronic hardware design including integrated circuits, embedded systems, and design automation tools. Advances in Hardware Design for Security and Trust offers self-contained tutorials within each chapter, as well as a presentation of recent advances. The relevance of each method in the context of the overall design and fabrication process is clearly articulated. Both qualitative analysis and quantitative experimental results to evaluate the significance of methods are presented. Both side-channel methods as well as front-channel techniques are covered. The authors emphasize methods that are ready for technology transition and commercialization. This book is intended for both researchers and industry practitioners. They will benefit from the tutorial style exposition of the topics along with advanced research results and emerging directions.

Table of Contents:
1. Introduction 2. Hardware Security In The Consumer Technology Industry 3. A Commercial EDA Perspective on Hardware Security, Safety, and Trust 4. Machine Learning Techniques for Detecting Hardware Trojans in ASIC designs 5. Next-Generation Semiconductor Reverse Engineering: Laser Delayering, Correlative Imaging, and Cloud-Enabled Image Analysis Techniques 6. Synthesis of Polymorphic Circuits for Hardware Security 7. Design Obfuscation and Performance Locking Solutions for Mixed-Signal, Analog and RF ICs 8. On-Chip Integrity, Reliability, and Aging Assurance Techniques for ICs 9. Deep Learning Side-Channel Attack: Challenges and Opportunities 10. Side Channel Attack Avoidance and Mitigation through Asynchronous Digital Design 11. Is ARM TrustZone trustable for confidentiality protection? 12. Security Verification for Next Generation SoCs 13. Cloud FPGA Accelerator Fingerprinting Using Communication Side-Channels 14. Enterprise Risk Management of Electronics and Computing Device Supply Chains

About the Author :
Ranga Vemuri is a Professor in Electrical and Computer Engineering and directs the Digital Design Environments Lab at the University of Cincinnati where served since 1989. His interests are in Hardware Trust, Correctness and Security, VLSI Design and Design Automation, and Reconfigurable Computing. His research has been funded by AFRL, DAGSI, DARPA, NSF, State of Ohio and various industries. He and his students have published over 300 papers and have received several Best Paper Awards and nominations. Prof. Vemuri co-authored two books and graduated 42 PhD and over 90 MS students. He served on the program committees of numerous international conferences and served as an Associate Editor of the IEEE Transactions on VLSI and as a Guest Editor of the IEEE Computer. John Emmert has been an Electrical Engineering Professor since 1999. His research has been funded by AFRL, DARPA, NSF, the US Congress, the State of Ohio and various industrial companies, and he currently has eight full and three provisional US patents, all related to integrated circuit design. He is the Director of the NSF Center for Hardware and Embedded Systems Security and Trust (CHEST) I/UCRC. He also served in the United States Air Force from 1989-2015. In the Air Force he held positions from UAV pilot to reserve wing commander, and after 26 years of service, he retired as a Colonel. He has been awarded the Air Force Legion of Merit and five Meritorious Service Medals.