Advanced Charge Trap Memory: Stack Design and Cell Characterization

This dissertation focuses on the understanding of advanced charge-trap memory with a goal toward optimized memory stack design. High quality Si3N4 and Al2O3 dielectrics, synthesized in the MAD system, have been developed and adopted as the tunnel dielectric and blocking layer, respectively, in SONOS-type NAND flash memory cells. A charge trapping MAD (Molecular-Atomic Deposition) nitride with high density of traps has been produced by detuning the original deposition recipe. In search of a optimized stack design, an all-silicon-nitride stack memory cell (based on SNNNS/MANNS structure) has been demonstrated with superior performance. We achieved low-voltage program/erase on aggressively scaled memory stacks, with relatively long retention and good cycling endurance. A two-stage programming technique (PASHEI) with high charge injection efficiency has also been demonstrated on NOR-type SNNNS flash cell. Ultra-low operating voltage has been achieved, and localized 2-bit/cell charge storage has been demonstrated. We have also studied the F-P trap energies in Al2O3/HfAl yOx thin films of various compositions, where these trap energies have been extracted by the use of a novel technique without prior knowledge of fitting parameters. Results have shown that the trap energy increases with the Al content in HfAlyOx, and the trend follows Bohr's hydrogen atom model, as the energy level is mediated by the dielectric constant of the HfAlyOx layer. These results suggest that HfAlyOx has great potential for use as a charge-trap medium in NAND-type flash memory cell. The tunability of the trap energy through composition control will enable the optimization of retention and/or program/erase efficiency to meet device requirements. The program/erase transient behavior of advanced NAND-type flash memory cell has been modeled and measured. In particular, charge transport of MINOS memory devices during the erase operation has been successfully modeled by the use of tunneling theories. In order to address issues associated with the model, a time-resolve transient current measurement has been employed to study transient programming behavior of the nanodot flash memory cell. We started with an equivalent circuit to study the current components of each layer of the dielectric stack, with the result verified by the time-resolved programming current measurement. The measurement setup and the proposed model can be used for evaluating the effectiveness of the blocking layer on charge retention as well as programming efficiency during the programming operation.