Systolic Arrays, Papers presented at the First INT Workshop on Systolic Arrays, Oxford 2-4 July 1986

This book contains the edited proceedings of the First International Workshop on Systolic Arrays. The workshop was the second in a series on topics in VLSI (the first being on Wafer Scale Integration), and brought together workers in the field of systolic arrays and related SIMD architectures from around the world. The papers in this volume have been selected to cover all major aspects of systolic arrays: design methodologies, simulation and formal synthesis, algorithms and architectures, applications and chip designs, testing and fault tolerance, wavefront arrays and SIMD alternatives. Systolic arrays - along with other parallel computer designs - are becoming important for many applications; there is currently a large research effort being devoted to them and commercial ICs are becoming available. Therefore this book is a very timely introduction to, and summary of, the present state of development. The editors: Dr Will Moore has been involved in research into VLSI architectures, including systolic arrays, for six years and has a special interst in regular arrays, testing, faut tolerance and very large circuits. He initiated the First International Workshop on Wafer Scale Integation in 1985 (Adam Hilger 1986) and is planning events on Hardware Accelerators and Designing for Yield. Andrew McCabe has been involved in integrated circuit design and appliactions for eleven years. For the last six years he has managed a VLSI architectures research and development team and has worked on the design of several systolic array ICs. His current interests include parallel processing, systolic algorithms and architecture, formal designmethods, fault tolerance and wafer scale integration. Dr Roddy Urquhart has worked on the research and development of systolic array architectures for four years. He is currently managing a development programme of high performance Ics for digital signal processing.

Table of Contents:
Prologue. Design Methods and Tools: VLSI Array Processors (S Y Kung). Synthesising systolic arrays using DIASTOL (P Gachet, B Joinnault & P Quinton). Efficient systolic arrays for the solution of Toeplitz systems - an illustration of the methodology for the construction of systolic architectures in VLSI (J-M Delosme & I Ipsen). The derivation and utilisation of bit level systolic array architectures (J McCanny and J McWhirter). Miss - a test-bed for systolic archtectures (S Kuppuswami and F Andre) Hearts - a dialect of the poker programming environment specialised to systolic computation (L Snyder) Use of real-time declarative language for systolic array design and simulation (N Halbwachs and D Pilaud). Exploring designs by circuit transformation (G Jones and W Luk). Applications: Semi-systolic maximum rate transversal filters with programmable coefficients (T Noll). The MA7170 systolic correlator, architecture and appliactions (B Christie). Systolic arrays over finite rings with applications to digital signal processing (S Bandyopadhyay, G Jullien and M Bayoumi). Systolic FFT processors (E Swartzlander). An efficient systolic array for distance computation required in a video-codec based on motion-detection (F Catthoor and H de Man). A systolic array for linearly constrained least-squares optimisation (T Shepherd and J McWhirter). On realizations of least-squares estimation and Kalman filtering by systolic arrays (M-J Chen and K Yao). Systolic solution of the algebraic path problem (Y Robert and D Trystram). Comparing long strings on a short systolic array (R Lipton and D Lopresti). A family of systolic arrays for relational database operations (Y-C Lin and F-C Lin). Fault Tolerance and Test: Yield modelling for fault tolerant VSLI arrays (P Franzon). Self-diagnosis of linear and mesh systolic arrays by signature comparison (S Su, M Cutler, M Wang and K Saluja). A hierarchical test strategy for self-organising fault tolerant arrays (R Evans and J McWhirter). Distributed structuring of processor arrays in the presence of faulty processors (I Koren and I Pomeranz). A protocol for asynchronous wavefront-computation arrays (F Distante and M G Sami). Algorithm reconfiguration techniques for gracefully degradable procesor arrays (J Fortes). More Flexible Architectures: Comparison of systolic and SIMD architectures for computer vision computations (P Dew and L Manning). The RPA as and intelligent transputer memory system in an Occam programming model (C Jesshope). The application and development of wavefront array processors for advanced front-end signal processing systems (C Ward and E Davie). Irregular wavefronts in data-driven, data-dependent computations (R Melhem). A reconfigurable processor array using LINC chip (W-T Lin and C-Y Chin). Dedicated systolic arrays as nodes in a data flow machine (S Bergman and D Tal). Epilogue. Index.