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Jakub Szefer

Jakub SzeferJakub Szefer's research interests are at the intersection of computer architecture and hardware security. Jakub's recent projects focus on security verification of processor architectures; hardware (FPGA) implementation of cryptographic algorithms, epecially post-quantum cryptographic (PQC) algorithms; Cloud FPGA security; designs of new Physically Unclonable Functions (PUFs); and leveraging physical properties of computer hardware for new cryptographic and security applications. Jakub's research is currently supported through National Science Foundation and industry donations. Jakub is a recipient of a 2017 NSF CAREER award. In the summer of 2013, he became an Assistant Professor of Electrical Engineering at Yale University, where he started the Computer Architecture and Security Laboratory (CAS Lab). Prior to joining Yale, he received Ph.D. and M.A. degrees in Electrical Engineering from Princeton University, where he worked with his advisor, Prof. Ruby B. Lee, on secure processor architectures. He received a B.S. with highest honors in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign. Read More Read Less

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1.
Security of FPGA-Accelerated Cloud Computing Environments
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AED402
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Hardback
Release:
03 Jan 2024
Language:
English
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2.
Principles of Secure Processor Architecture Design
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AED288
Binding:
Paperback
Release:
18 Oct 2018
Language:
English
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Principles of Secure Processor Architecture Design
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AED586
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Release:
18 Oct 2018
Language:
English
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Security of FPGA-Accelerated Cloud Computing Environments
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AED282
Binding:
Paperback
Release:
04 Jan 2025
Language:
English
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5.
Principles of Secure Processor Architecture Design
Publisher: Morgan & Claypool
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AED231
Binding:
Digital (delivered electronically)
Release:
18 Oct 2018
Language:
English
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