VLSI Design of Neural Networks

The early era of neural network hardware design (starting at 1985) was mainly technology driven. Designers used almost exclusively analog signal processing concepts for the recall mode. Learning was deemed not to cause a problem because the number of implementable synapses was still so low that the determination of weights and thresholds could be left to conventional computers. Instead, designers tried to directly map neural parallelity into hardware. The architectural concepts were accordingly simple and produced the so­ called interconnection problem which, in turn, made many engineers believe it could be solved by optical implementation in adequate fashion only. Furthermore, the inherent fault-tolerance and limited computation accuracy of neural networks were claimed to justify that little effort is to be spend on careful design, but most effort be put on technology issues. As a result, it was almost impossible to predict whether an electronic neural network would function in the way it was simulated to do. This limited the use of the first neuro-chips for further experimentation, not to mention that real-world applications called for much more synapses than could be implemented on a single chip at that time. Meanwhile matters have matured. It is recognized that isolated definition of the effort of analog multiplication, for instance, would be just as inappropriate on the part ofthe chip designer as determination of the weights by simulation, without allowing for the computing accuracy that can be achieved, on the part of the user.

Table of Contents:
Guide Lines to VLSI Design of Neural Nets.- (Junction) Charge-Coupled Device Technology for Artificial Neural Networks.- Analog Storage of Adjustable Synaptic Weights.- Precision of Computations in Analog Neural Networks.- Architectures for a Biology-Oriented Neuroemulator.- Pulsed Silicon Neural Networks - Following the Biological Leader -.- ASICs for Prototyping of Pulse-Density Modulated Neural Networks.- VLSI Design of an Associative Memory based on Distributed Storage of information.- Silicon Integration of Learning Algorithms and other Auto-Adaptive Properties in a Digital Feedback Neural Network.- Fast Design of Digital Dedicated Neuro Chips.- Digital Neural Network Architecture and Implementation.- Toroidal Neural Network: Architecture and Processor Granularity Issues.- Unified Description of Neural Algorithms for Time-Independent Pattern Recognition.- Design of a 1st Generation Neurocomputer.- From Hardware to Software: Designing a “Neurostation”.