Self-Testing VLSI Design

A distinctive feature of modern computer equipment development is the continuous increase in functionality and complexity of computer components. As a result of these advances, very large-scale integration (VLSI) circuits have found extensive application in the manufacture of computer products, personal computers included. Among a variety of recently evolved VLSI design technologies, the self-test VLSI design has gained particular prominence. The present study provides a current review on the problems of self-test VLSI design. A summary is given on self-test VLSI design results that have been obtained by scientists in leading scientific centres for computer integrated circuits. Emphasis is placed on the theoretical fundamentals of designing self-test VLSI building blocks, such as built-in test generators and output response analyzers. Particular attention is paid to: structural design of self-test VLSI circuits; design of universal modules for self-test VLSI circuits; and examination of the VLSI circuits for signature testability. It has been demonstrated that the design-for-testability techniques employed by this method provide ideal conditions for the straightforward implementation of self-test concepts. The work should prove useful for all those interested in both the basic facts and current research in this field.

Table of Contents:
Part 1 VLSI design: achievements in microelectronics; VLSI design procedure; self-testing VLSI chips. Part 2 VLSI testability design approaches: VLSI testability design feature; storage element state scan technique; level sensitive scan desing (LSSD); random access scan technique; VLSI design by boundary scan technique. Part 3 Self-testing VLSI structured design: self-testing VLSI using scan path; ring VLSI self-test; use of general-purpose modules for self-test VLSI design; self-testing microcomputers. Part 4 Pseudorandom test pattern generators: pseudorandom test pattern generators: pseudorandom sequences; generators of uniformaly distributed pseudorandom test sequences; pseudorandom test pattern generators. Part 5 Pseudorandom and related sequence generators: design of pseudorandom test sequence generator. Part 6 Random testing: probabilistic analysis techniques for digital circuits; test sequence length calculation; automatic search for optimum probability. Part 7 Pseudorandom testing: pseudorandom sequences as the test sequences of the circuit; structured VLSI design with built-in random and pseudorandom tests. Part 8 Exhaustive testing: complexity of exhaustive test sequence generator design; iterative algorithm for exhaustive test generation. Part 9 Signature analysis: signature analysis as a binary polynomial division algorithm; multi-functional signature analyzer. Part 10 Signature analysis efficiency: estimation of signature analysis efficiency. Part 11 Evaluation techniques for regular binary sequence signatures: evaluation of regular sequence signatures; a technique for calculating periodic sequence signatures. Part 12 Multi-line compression schemes: design of parallel signature analyzers; state count testing. Part 13 Analysis of bilbo-PSA efficiency: equivalent PSA circuits with internal and external XOR gates; PSA efficiency testing by software simulation. Part 14 PSA design for VLSI self test: an efficient parallel signature analyzer; two-stage PSA design. Part 15 PSA with T-flip-flops design and analysis: parallel signature analyzer with T-flip-flops as storage elements. Part 16 Signature testability: signature as a function of multiple variables; generalized condition for signature testability. Part 17 Evaluation of signatures: analytical evaluation of Boolean function signatures; finding signatures for reciprocal polynomials. Part 18 Signature testability of VLSI chips: signature testability of faults at primary nodes of combinational circuit; analytic approach to evaluating signatures and signature testability of faults by PSA.