Logic and Architecture for Silicon Compilers: International Workshop Proceedings

VLSI synthesis is a subject that is moving rapidly from the research laboratory into the industrial environment, and it is generally accepted that synthesis will gradually become the dominant design technique, surpassing conventional manual techniques. This book provides a timely overview on the various systems for logical and architectural synthesis for VLSI. It discusses the algorithms and techniques necessary for a synthesis system that is competitive with current design techniques for integrated circuits. The book covers both low-level logic synthesis techniques and higher-level architectural techniques, both of which are increasing in practical importance, since they will form the basis of the next generation of CAD software for integrated circuits. Three main topics are addressed: The first concerns two-level and multi-level synthesis. It includes PLA and PAL implementation as well as standard cell and compiled cell based synthesis. The second concerns controller synthesis with emphasis on optimisation methods. The third deals with high level synthesis (resource allocation, scheduling) as applied to DSP systems and processors consisting of controllers and data paths.

Table of Contents:
1. Two Level and Multilevel Synthesis. An alternative to Espresso II (P. Sicard, C. Duff). Timing optimization in a logic synthesis system (K. Keutzer, M. Vancura). Timing estimation for netlist performance improvement (C. Kingsley). Highly wireable multilevel synthesis with compiled cells (R. Leveugle, G. Saucier). TECHMAP: Technology mapping with delay and area optimization (C.R. Morrison et al.). A critique of the gatemap logic synthesis system (E.B. Pitty). DECO: A device compilation system (B.A. Dalio, J.E. Savage). Applications of a logic synthesizer for direct conversion of PLA's and Boolean equations into standard library cells using CAE schematic capture tools (R.J. Lenski, G. Schneir). Logic synthesis on PALS (P. Sicard). Multi-level Boolean optimization for incompletely specified Boolean functions in PHIFACT (C. Ykman-Couvreur). II. Controller Synthesis. Controller synthesis in LOGSYN (A. Postula et al.). Controller synthesis in the ASYL system (M. Crastes et al.). On control-step assignment in a transformational synthesis system: C: Expressions and their algebra (R.R. Vemuri, C.A. Papachristou). Synthesis of speed-independent circuits using `Set-memory' elements (C. Berthet, E. Cerny). III. High Level Synthesis. High-level synthesis benchmark results using a global scheduling algorithm (P.G. Paulin, J.P. Knight). Data path and control synthesis in the CADDY system (H. Kramer et al.). Hardwired data path synthesis for high speed DSP systems with the CATHEDRAL-III compilation environment (S. Note et al.). Design of an application specific microprocessor (R. Leveugle, M. Soueidan). Designing a flexible 2910 microcode sequencer using high-level design tools (F.T. Riherd). Optimization-based synthesis of multiprocessor chips for digital signal processing, with CATHEDRAL II (G. Goossens et al.). Efficient design of systems on silicon with PIRAMID (J.A. Huisken et al.). EASY: Multiprocessor architecture optimisation (L. Stok, R. van den Born).