Formal Methods for Very Large Scale Integration Design
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Formal Methods for Very Large Scale Integration Design

Formal Methods for Very Large Scale Integration Design

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About the Book

These lecture notes contain an overview of an exciting new field of research, formal methods which give the VLSI designer a firm foundation and useful tools for developing integrated circuits. Such methods allow the possibility of systematic verification in the early phases of the design process. By verifying high level descriptions of the design before concerning themselves with low level details, designers can avoid wasting time implementing circuits that would later be discarded. Obviously it can be very expensive to locate and correct errors found in the later stages of a project, especially if correcting these errors requires extensive, global changes to the design. Furthermore, the long turn-around time for circuit fabrication makes it attractive to use techniques which uncover errors at an early phase of the design. The summer school where these lectures were given was held in Denmark in June 1990, and consisted of six series of lectures, each presenting a distinct formal method.

Table of Contents:
Circuit Design in Ruby. Composition and Inverse. Lists and Tuples. Rows and Columns. Transposition and Zips. Sequential Circuits. A Systolic Correlator. Butterfly Networks. The Fourier Transform. Synchronized Transitions. Invariants. Examples. Tools. Synchronous Realizations. Mechanical Verification. Abstraction Functions. Delay Insensitive Realizations. Verifying SECD in HOL. Introducing HOL. The Abstract SECD Machine. Designing the SECD. SECD Formal Specification. Verification of the SECD Design. Formal Ruby. Signals and Strong Typing. Pure Ruby. Implementation. Formal System Design. Modelling Digital Behaviour. Goal-Directed Design. Abstraction. Top-Down Design. Synthesis of Asynchronous VLSI Circuits. Communicating Hardware Processes. The Object Code, Production Rules. The Compilation Method. Case Study: Distributed Mutual Exclusion. A Formal Introduction to a Simple HDL. Hardware Verification. The Boyer-Moore Logic. Introduction to Circuit Generators. Boxlist Syntax. Hardware Interpreters. A Simple Circuit Generator. A Heuristically Guided Adder Generator. An ALU Generator. Translating our HDL into a Commercial CAD Language.


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Product Details
  • ISBN-13: 9780444888587
  • Publisher: Elsevier Science & Technology
  • Publisher Imprint: Elsevier Science Ltd
  • Height: 220 mm
  • ISBN-10: 0444888586
  • Publisher Date: /11/1990
  • Binding: Hardback


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