Digital Logic and Microprocessor Design with Interfacing, International Edition

Learn how to design digital logic circuits, specifically combinational and sequential circuits, with DIGITAL LOGIC AND MICROPROCESSOR DESIGN WITH INTERFACING, 2E. This book teaches you how to put these two types of circuits together to form both dedicated and general-purpose microprocessors. This book’s unique approach combines the use of logic principles with the building of individual components to create data paths and control units. With this book you are able to design simple microprocessors, implement them in real hardware, and interface them to real-world devices. Watch the exciting process as your own microprocessor comes to life in real hardware using the knowledge and skills you gain from DIGITAL LOGIC AND MICROPROCESSOR DESIGN WITH INTERFACING, 2E.

Table of Contents:
Preface. 1. INTRODUCTION TO MICROPROCESSOR DESIGN. Overview of Microprocessor Design. Design Abstraction Levels. Examples of a 2-to-1 Multiplexer. Introduction to Hardware Description Language. Synthesis. Going Forward. Problems. 2. FUNDAMENTALS OF DIGITAL CIRCUITS. Binary Numbers. Negative Numbers. Binary Switch. Basic Logic Operators and Logic Expressions. Logic Gates. Truth Tables. Boolean Algebra and Boolean Equations. Minterms and Maxterms. Canonical, Standard, and non-Standard Forms. Digital Circuits. Designing a Car Security System. Verilog and VHDL Code for Digital Circuits. 3. COMBINATIONAL CIRCUITS. Analysis of Combinational Circuits. Synthesis of Combinational Circuits. Minimization of Combinational Circuits. Timing Hazards and Glitches. BCD to 7-Segment Decoder. Verilog and VHDL Code for Combinational Circuits. Problems. 4. STANDARD COMBINATIONAL COMPONENTS. Signal Naming Conventions. Multiplexer. Adder. Subtractor. Adder-Subtractor Combination. Arithmetic Logic Unit. Decoder. Tri-state Buffer. Comparator. Shifter. Multiplier. Problems. 5. SEQUENTIAL CIRCUITS. Bistable Element. SR Latch. Car Security System--Version 2. SR Latch with Enable. D Latch. D Latch with Enable. Verilog and VHDL Code for Memory Elements. Clock. D Flip-Flop. D Flip-Flop with Enable. Description of a Flip-Flop. Register. Register File. Memories. Shift Registers. Counters. Timing Issues. Problems. 6. FINITE-STATE MACHINES. State Diagrams, Finite-State Machine (FSM) Models. Analysis of Finite-State Machines. Synthesis of Finite-State Machines. Optimizations for FSMs. FSM Construction Examples. Verilog and VHDL Code for FSM Circuits. Problems. 7. DEDICATED MICROPROCESSORS. Need for a Datapath. Constructing the Datapath. Constructing the Control Unit. Constructing the Complete Microprocessor. Dedicated Microprocessor Construction Examples. Verilog and VHDL Code for Dedicated Microprocessors. Problems. 8. GENERAL-PURPOSE MICROPROCESSORS. Overview of the CPU Design. The EC-1 General-Purpose Microprocessor. The EC-2 General-Purpose Microprocessor. Extending the EC-2 Instruction Set. Using and Interfacing the EC-2. Pipelining. Verilog and VHDL Code for General-Purpose Microprocessors. Problems. 9. INTERFACING MICROPROCESSORS. Multiplexing 7-Segment LED Display. Issues with Interfacing Switches. 3×4 Keypad Controller. PS2 Keyboard and Mouse. RS-232 Controller for Bluetooth Communication. Liquid-Crystal Display Controller. VGA Monitor Controller. A/D Controller for Temperature Sensor. I2C Bus Controller for Real-Time Clock. Problems. 10. APPENDIX A – XILINX DEVELOPMENT TUTORIAL. Starting ISE. Creating a New Schematic Source File. Creating a New Verilog or VHDL Source File. Setting the Top-Level Module Design File. Mapping the I/O Signals. Synthesis and Implementation. Programming the Circuit to the FPGA. Problems. 11. APPENDIX B – ALTERA DEVELOPMENT TUTORIAL. Starting Quartus. Using the Graphic Editor. Managing Files in a Project. Analysis and Synthesis. Creating and Using a Logic Symbol. Mapping the I/O Signals. Fitting the Netlist and Pins to the FPGA. Programming the Circuit to the FPGA. Problems. 12. APPENDIX C – VERILOG SUMMARY. Basic Language Elements. Behavioral Model. Dataflow Model. Structural Model. 13. APPENDIX D – VHDL SUMMARY. Basic Language Elements. Behavioral Model--Sequential Statements. Dataflow Model--Concurrent Statements. Structural Model--Concurrent Statements. Conversion Routines. Index.