Computer Hardware Description Languages and Their Applications: Proceedings of the 11th IFIP WG10.2 International Conference, Ottawa, Canada, 26-28 April 1993

Hardware description languages (HDLs) have established themselves as one of the principle means of designing electronic systems. The interest in and usage of HDLs continues to spread rapidly, driven by the increasing complexity of systems, the growth of HDL-driven synthesis, the research on formal design methods, and many other related advances. This research-oriented publication makes a contribution to further developments in the field. The following topics are explored in depth: BDD-based system design and analysis; system level formal verification; formal reasoning on hardware; languages for protocol specification; VHDL; HDL-based design methods; high level synthesis; and text/graphical HDLs. There are short papers covering advanced design capture and recent work in high level synthesis and formal verification. In addition, several invited presentations on key issues discuss and summarize recent advances in real time system design, automatic verification of sequential circuits and languages for protocol specification.

Table of Contents:
Part 1 Invited presentation: real time distributed systems, M.R. Barbacci. Part 2 BDD-based design and analysis techniques: verification of the futurebus + cache coherence protocol, E.M. Clarke et al; exploiting symbolic traversal techniques for efficient process algebra manipulation (PRAM), P. Camurati et al. Part 3 HDL-based design methods: HW/SW co-design with PRAMs using codes, K. Buchenrieder et al; prevail-DM - a framework-based environment for formal hardware verification, F.R. Wagner. Part 4 Synthesis and verification: a rewriting based method for the formal verification of microprocessors, M. Allemand; reasoning about the VHDL standard logic package signal data type, J.W. Gambles and P.J. Windley; an efficient data-path synthesis based on algorithmic description under the constraints of time and area, X.-J. Xu and M. Ishizuka. Part 5 Invited presentation: automatic verification of sequential circuit designs, E.M. Clarke. Part 6 Protocol specification: toward a basis for protocol specification and process decomposition, K. Rath and S.D. Johnson; integrating SDL and VHDL for system-level hardware design, W. Glunz et al. Part 7 Formal reasoning about regular structures: reasoning about array structures using a dependently typed logic, A. Dent and K. Hanna; VHDL description and formal verification of systolic multipliers, L. Pierre; transformational rewriting with ruby, R. Sharp and O. Rasmussen. Part 8 High level synthesis: a representation for the binding of RT-component functionality to HDL behavior, R.P. Ang and N.I. Dutt; performance specification and measurement, R. Mandayam and R. Vemuri. Part 9 VHDL: system-level specification and design using VHDL - a case study, W. Ecker and S. Marz; a denotational definition of the VHDL simulation kernel, K.C. Davis; checking DFT rules with a VHDL simulator, W. Glunz and T. Rossel; parameterized VHDL entities for the simulation of hybrid circuits, M. Ryba et al. (Part Contents).