Computer Aided Design Accelerators: Proceedings of the International Workshop on Hardware Accelerators for C.A.D., Oxford, 20-21 September 1989

The University of Oxford was the setting for the workshop where the papers in this book were first presented. Authors from around the world have contributed papers covering theory, practical applications and commercial products, with particular emphasis on VLSI implementations and applications. They put hardware accelerators in their correct context alongside emerging software algorithms which also claim useful speed advantages. Forthcoming commercial developments and research work are presented by the leaders in the field.

Table of Contents:
Commercial Systems. Changing the Hardware Accelerator Game (T. Saxe, P. Offredi). Accelerator Techniques for System Design (I. Gander). Design Considerations for a Commercial Accelerator for Digital Systems Design (T. Carlstedt-Duke). Performance Issues I. Scalable High Performance CAD Accelerators (R.J. Smith). Performance Issues in a Compiled-Code Hardware Accelerator (D.M. Lewis). An Optimized Hardware Accelerator for Digital Logic Simulation (S. Fehr, S.A. Szygenda). Simulation and Test. Modeling and Simulation of Functional Memory Blocks in the MARS Accelerator (P. Agrawal, C. Moturu, R. Tandundjian). The Event Processor - A General Purpose Accelerator (N. Coleman, T. Ambler). Design and Analysis of a Hardware Automatic Test Generation System (N.A. Zaida, S.A. Szygenda). Acceleration of ATPG by Making Use of Hierarchy (C.A. Nijinda, W.R. Moore). Using Transputers. A Transputer Based VLSI Workstation (S. Christian, A. Gray). Distributed Simulation of Digital Designs on a Multi-Transputer Net (W. Hahn et al.). Distributed Design Rule Checking on a Transputer-Based Parallel Machine (J. Medou Z.). ESimAc - A Hardware Accelerator for Mixed-Mode Simulation (K. Jacoby, E. Pfeuffer, H. Thinschmidt). Graphics & Knowledge Processing. PAPRICA - A Parallel Architecture for VLSI CAD (G. Conte et al.). Use of a Parallel Cellular Processing System for Fast Generation of Perspective Plots (J.H. Beyer, R.M. Lougheed). The WAVE Model for Advanced Knowledge Processing (P.S. Sapaty). Layout Acceleration. MANURE2 - A Second Generation Accelerator for PCB Routing (D. Edwards). LARA - A Layout Accelerator Based on Reduced Array Architecture (C.P. Ravikumar, S. Sastry). A Multi-Layer Channel Router (M. van Veelen, A.J.W.M. ten Berg). Performance Issues II. A Parallel Approach to Three-Layer Channel Routing (C.P. Ravikumar, S. Sastry). Parallel Mixed-Level Simulation Using Virtual Time (J.V. Briner, J.L. Ellis, G. Kedem). Distributed Demand-Driven Logic Simulation (S.P. Smith, M.R. Mercer). Author Index .