Electronic Devices Architectures for the NANO-CMOS Era

About the Book

In this book, internationally recognized researchers give a state-of-the-art overview of the electronic device architectures required for the nano-CMOS era and beyond. Challenges relevant to the scaling of CMOS nanoelectronics are addressed through different core CMOS and memory device options in the first part of the book. The second part reviews new device concepts for nanoelectronics beyond CMOS. The book covers the fundamental limits of core CMOS, improving scaling by the introduction of new materials or processes, new architectures using SOI, multigates and multichannels, and quantum computing.

Table of Contents:
CMOS Nanoelectronics. Reaching the End of the Roadmap: Core CMOS: Physical and Technological Limitations of NanoCMOS Devices to the End of the Roadmap and Beyond. Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization. Devices Structures and Carrier Transport Properties of Advanced CMOS using High Mobility Channels. High-kappa Gate Dielectrics. Fabrication of Source and Drain- Ultra Shallow Junction. New Interconnect Schemes: End of Copper, Optical Interconnects? Memory Devices: Technologies and Key Design Issues for Memory Devices. FeRAM and MRAM Technologies. Advanced Charge Storage Memories: From Silicon Nanocrystals to Molecular Devices. New Concepts for Nanoelectronics. New Paths Added to CMOS Beyond the End of the Roadmap: Single Electron Devices and Applications. Electronic Properties of Organic Monolayers and Molecular Devices. Carbon Nanotube Electronics. Spin Electronics. The Longer Term: Quantum Information Processing and Communication.

About the Author :

Simon Deleonibus (MSc 1979, PhD 1982, Paris University) was with Thomson Semiconducteurs, Grenoble, France, from 1981 to 1986 in device engineering development and then production. In 1986 he was with CEA LETI advanced device and process modules research specialising in CMOS and flash memories applications. From 1998 to 2008 he was the director of the Electronic Nanodevices Laboratory with 55 researchers under his charge. Since 2008, he is the chief scientific director of Silicon Technologies of LETI. He owns the initial patent on contact plug principle, widely used as a standard process by the semiconductor industry. He actualised the first 20-nm gate length MOSFET, the world's smallest transistor, in June 1999. He is the editor of IEEE Transactions on Electron Devices and a member of the International Technology Roadmap of Semiconductors (ITRS), of the board of directors of the Nanosciences Foundation and of The European Research Council Engineering Panel. A Fellow of the IEEE, he is its distinguished lecturer. He is also the research director of the French CEA.

Review :
"This book offers an excellent insight into the micro-to-nano transition that the electronics industry is currently engaged in. The different chapters clearly illustrate the latest stages of evolution of the 'classical' silicon transistor and explore next-generation devices which are likely to be its successor. It is an excellent reference for scientists and students interested in the future of electronics." --Prof. Jean-Pierre Colinge, Tyndall National Institute, Ireland "The internationally recognized authors of this book provide a fascinating, information-packed reference for scientists, engineers and students interested in ultimately scaled CMOS and the emerging new 'Beyond CMOS' device technologies. By encompassing this broad technological vista in a single volume, the authors provide unique perspectives into the current issues and future challenges facing the semiconductor industry as we expand information-processing technologies to completely new applications." --Dr Jim Hutchby, Semiconductor Research Corporation, USA "This unique book is a must for everybody active in the field and/or interested in the technology of state-of-the-art and future electronic devices. Great work about small things." --Prof. Cor Claeys, IMEC, Leuven , Belgium