Real-Time Multi-Chip Neural Network for Cognitive Systems: (River Publishers Circuits and Systems)

Real-Time Multi-Chip Neural Network for Cognitive Systems presents novel real-time, reconfigurable, multi-chip SNN system architecture based on localized communication, which effectively reduces the communication cost to a linear growth. The system uses double floating-point arithmetic for the most biologically accurate cell behavior simulation, and is flexible enough to offer an easy implementation of various neuron network topologies, cell communication schemes, as well as models and kinds of cells. The system offers a high run-time configurability, which reduces the need for resynthesizing it. In addition, the simulator features configurable on- and off-chip communication latencies as well as neuron calculation latencies. All parts of the system are generated automatically based on the neuron interconnection scheme in use. The simulator allows exploration of different system configurations, e.g. the interconnection scheme between the neurons, the intracellular concentration of different chemical compounds (ions), which affect how action potentials are initiated and propagate.

About the Author :
Amir Zjajo received M.Sc. and DIC degrees from the Imperial College London, London, U.K., in 2000 and a PhD from Eindhoven University of Technology, Eindhoven, The Netherlands in 2010, all in Electrical Engineering. In 2000, he joined Philips Research Laboratories as a member of the research staff in the Mixed-Signal Circuits and Systems Group. From 2006 until 2009, he was with Corporate Research of NXP Semiconductors as a Senior Research Scientist. He joined Delft University of Technology in 2009. In 2018, he co-founded Innatera Nanosystems to commercialize bionic signal processing technology. Dr. Zjajo has published more than 80 papers in referenced journals and conference proceedings, and holds more than 10 US patents or patent pending. He is the author of the books Brain-Machine Interface: Circuits and Systems (Springer, 2016), Low-Voltage High-Resolution A/D Converters: Design, Test and Calibration (Springer, 2011, Chinese translation, China Machine Press, 2015) and Stochastic Process Variations in Deep-Submicron CMOS: Circuits and Algorithms (Springer, 2014). Rene van Leuken is a staff member of the Circuits and Systems Group at the Delft University of Technology in the Netherlands. His research interests include Algorithms and Architectures, ESL design, high level synthesis, VLSI design methodology, System model methodology, System modeling and optimization, VLSI System - and Complex Computing Blocks realization, with application areas including neuromorphic processing hardware fabrics (CNN, SNN), image processing and data stream processing.