Cryptographic Hardware and Embedded Systems -- CHES 2010: 12th International Workshop, Santa Barbara, USA, August 17-20,2010, Proceedings(Security and Cryptology)

Since 1999, the workshop on Cryptographic Hardware and Embedded Systems (CHES) is the foremost international scienti?c event dedicated to all aspects of cryptographic hardware and security in embedded systems. Its 12th edition was held in Santa Barbara, California, USA, August 17-20, 2010. Exceptionally this year, it was co-located with the 30th International Cryptology Conference (CRYPTO). This co-location provided unique interaction opportunities for the communities of both events. As in previous years, CHES was sponsored by the International Association for Cryptologic Research (IACR). The workshopreceived 108 submissions, from 28 di?erent countries,of which the Program Committee selected 30 for presentation. Each submission was - viewed by at least 4 committee members, for a total of 468 reviews. Two invited talks completed the technical program. The ?rst one, given by Ivan Damg? ard and Markus Kuhn, was entitled "Is Theoretical Cryptography Any Good in Practice?", and presented jointly to the CRYPTO and CHES audiences, on Wednesday, August 18, 2010. The second one, given by Hovav Shacham, was entitled "Cars and Voting Machines: Embedded Systems in the Field. " The Program Committee agreed on giving a best paper award to Alexandre Berzati, C' ecile Canovas-Dumas and Louis Goubin, for their work "Public Key Perturbation of Randomized RSA Implementations. " These authors will also be invitedtosubmitanextendedversionoftheirpapertotheJournalofCryptology, together with the authors of two other contributions. First, Jean-Philippe - masson,LucaHenzen,WilliMeierandMar' ?aNaya-Plasencia,authorsof"Quark: aLightweightHash. "Second,LucaHenzen,PietroGendotti,PatriceGuillet,- rico Pargaetzi, Martin Zoller and Frank K.

Table of Contents:
Low Cost Cryptography.- Quark: A Lightweight Hash.- PRINTcipher: A Block Cipher for IC-Printing.- Sponge-Based Pseudo-Random Number Generators.- Efficient Implementations I.- A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over .- Co-Z Addition Formulæ and Binary Ladders on Elliptic Curves.- Efficient Techniques for High-Speed Elliptic Curve Cryptography.- Side-Channel Attacks and Countermeasures I.- Analysis and Improvement of the Random Delay Countermeasure of CHES 2009.- New Results on Instruction Cache Attacks.- Correlation-Enhanced Power Analysis Collision Attack.- Side-Channel Analysis of Six SHA-3 Candidates.- Tamper Resistance and Hardware Trojans.- Flash Memory ‘Bumping’ Attacks.- Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection.- When Failure Analysis Meets Side-Channel Attacks.- Efficient Implementations II.- Fast Exhaustive Search for Polynomial Systems in .- 256 Bit Standardized Crypto for 650 GE – GOST Revisited.- Mixed Bases for Efficient Inversion in and Conversion Matrices of SubBytes of AES.- SHA-3.- Developing a Hardware Evaluation Method for SHA-3 Candidates.- Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs.- Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures.- XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework.- Fault Attacks and Countermeasures.- Public Key Perturbation of Randomized RSA Implementations.- Fault Sensitivity Analysis.- PUFs and RNGs.- An Alternative to Error Correction for SRAM-Like PUFs.- New High Entropy Element for FPGA Based True Random Number Generators.- The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.-New Designs.- Garbled Circuits for Leakage-Resilience: Hardware Implementation and Evaluation of One-Time Programs.- ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware.- Side-Channel Attacks and Countermeasures II.- Provably Secure Higher-Order Masking of AES.- Algebraic Side-Channel Analysis in the Presence of Errors.- Coordinate Blinding over Large Prime Fields.