Vector Logic Computing

This book creates a non-processor economy vector logic in-memory computing based on read-write transactions on logical vectors, truth tables, and matrices. In-memory vector logic is a harmonic relationship between a model and an algorithm that aims to reduce time and energy in modeling for simulation by using additional space and matter. Vector logic is an ideal form of representation of functions and structures for modelling and simulating social and physical processes. Modeling without simulation is a prompt-computing for creating a comprehensive testing map of any functionality or structure on a logical vector. Intelligent computing is here the integration of classical and artificial intelligence mechanisms for modeling and simulation, using vector-logical and matrix models to process functions and structures. The book first discusses the development of smart vector logic data structures to reduce the computational complexity of simulation algorithms. Then it explores the creation of mechanisms for vector logic modeling and testing, leveraging truth tables and matrices built on a logical vector. After that, the author goes on to cover the following: vector testing of logic circuits by simulating faults as addresses of logical vector bits; vector testing of graph structures by simulating transition faults as truth table addresses, and vector logic in-memory computing of unitary-encoded big data as truth table addresses. The book then explores the logical vector modeling for the simulation of social processes via unitary pattern encoding on the universe primitives. The goal of cyber-social vector logic computing is energy-effective monitoring and moral management of cyber-social processes and phenomena. Vector logic is a functional and structural relationship for in-memory computing, which forms an exponentially redundant data structure in memory to minimize its processing time and energy. The original vector logic mechanisms are implemented in the MOSI cloud service – Modeling for Simulation, written in Python, for simulating good-value states and faults, as addresses for logical circuits, functionalities, and structures. The book can be helpful for specialists in the field of big data prompt computing, including social and physical processes, as well as for engineers involved in testing digital GL, RTL, and system-level projects, automatic test generation, and good-value and fault address simulation. The theory and practice of vector-logical computing, algorithms, models, mechanisms, and codes are an original development to create energy- and time-saving processor-less new computing in memory.

Vladimir Hahanov was born in USSR in 1953. He is Doctor of Science, Professor of Computer Engineering Faculty, Design Automation Department, Kharkov National University of Radio Electronics, Ukraine. R&D fields: Design and Test of computers, Test Generation and Fault Simulation for SoC, Quantum memory-driven computing, Cyber Physical & Cyber Social Computing, Pattern Recognition & Machine Learning Computing, Digital Smart Cyber University, Cloud-Driven Traffic Control, Vector-Logic Computing. Previous positions: Acting Science Vice-Rector (2016), Dean of Computer Engineering Faculty (2003-2017). Supervisor for 4 Doctor of Science, 36 PhD's, and 150 more engineers for 27 countries. General Chair of IEEE East-West Design & Test Symposium for 23 Years since 2003. Author of 650+ publications and 25 textbooks, 5 patents and 212 Scopus-indexed papers. H-index is 16, 1155 citations by 734 documents. Prof. Hahanov is IEEE Senior Member since 2010, IEEE Computer Society Golden Core Member, SAE Member and IFAC Member.