Processor Microarchitecture: An Implementation Perspective(Synthesis Lectures on Computer Architecture)

This lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular support to decoding x86 instructions. The next chapter presents the allocation stage and pays special attention to the implementation of register renaming. Afterward, the issue stage is studied. Here, the logic to implement out-of-order issue for both memory and non-memory instructions is thoroughly described. The following chapter focuses on the instruction execution and describes the different functional units that can be found in contemporary microprocessors, as well as the implementation of the bypass network, which has an important impact on the performance. Finally, the lecture concludes with the commit stage, where it describes how the architectural state is updated and recovered in case of exceptions or misspeculations. This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture. It is also intended for practitioners in the industry in the area of microprocessor design. The book assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execution, cache memories, and virtual memory. Table of Contents: Introduction / Caches / The Instruction Fetch Unit / Decode / Allocation / The Issue Stage / Execute / The Commit Stage / References / Author Biographies

Table of Contents:
Introduction.- Caches.- The Instruction Fetch Unit.- Decode.- Allocation.- The Issue Stage.- Execute.- The Commit Stage.- References.- Author Biographies.

About the Author :
Antonio Gonzalez received his Ph.D. degree from the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain, in 1989. He is the founding director of the Intel Barcelona Research Center, started in 2002, whose research focuses on computer architecture. He has been a faculty member of the Computer Architecture Department of UPC since 1986 and became a full professor in 2002. Antonio has filed over 40 patents, has published over 300 research papers, and has given over 80 invited talks in the areas of computer architecture and compilers. He has served as an Associate Editor of several IEEE and ACM journals, has been a member of the program committee of numerous symposia, the program chair for some of them, including ISCA, MICRO, HPCA, ICS, and ISPASS, and the general chair for MICRO. Antonio's awards include the award to the best student in computer engineering in Spain graduating in 1986, the 2001 Rosina Ribalta Award as the advisor of the best PhD project in Information Technology and Communications, the 2008 Duran Farrell Award for research in technology, and the 2009 Aritmel National Award of Informatics to the Computer Engineer of the Year. Fernando Latorre received his M.S. degree from the University of Zaragoza, Spain, in 2001 and his Ph.D. degree from the Universitat Politecnica de Catalunya (UPC), Barcelona, Spain, in 2009. His thesis focused on efficiently exploiting instruction level parallelism and thread level parallelism using adaptive multithreaded/multicore architectures. Fernando joined the Intel Barcelona Research Center in 2003 where he is a Senior Research Scientist, and he is also a member of the Architectures and Compilers research group of the UPC. His research interests range from power-efficient architectures to co-designed virtual machines and parallel processors. Fernando holds 2 patents, has filed several more, and has published more than 10 research papers in the area of computer architecture. He has served as a reviewer for numerous ACM and IEEE conferences and symposia, and was also a program committee member for WEED 2010 and ISCA 2011. In 2008, he received the Duran Farrell Award for research in technology. M.Sc. and Ph.D. degrees from the Computer Science Department of the University of Rochester, NY, in 2000 and 2005, respectively. His thesis focused on increasing the energy efficiency of adaptive architectures. In 2003, Grigorios joined the Intel Barcelona Research Center as a Senior Research Scientist. He is also a member of the Architectures and Compilers research group of the Universitat Politecnica de Catalunya, Barcelona, Spain, where he remains until today. His research interests include power-efficient architectures, parallel architectures, dynamic optimization, and operating systems, among others. Grigorios holds 6 patents and has published more than 20 research papers in the area of computer architecture and distributed systems. He has served as a reviewer for numerous ACM and IEEE conferences and symposia, and was also the architecture track program chair for IPDPS 2009. In 2008, he received the Duran Farrell Award for research in technology.