Computer Organization and Design: The Hardware/Software Interface

The performance of software systems is dramatically affected by how well software designers understand the basic hardware technologies at work in a system. Similarly, hardware designers must understand the far reaching effects their design decisions have on software applications. For readers in either category, this classic introduction to the field provides a deep look into the computer. It demonstrates the relationship between the software and hardware and focuses on the foundational concepts that are the basis for current computer design. Using a distinctive learning by evolution approach the authors present each idea from its first principles, guiding readers through a series of worked examples that incrementally add more complex instructions until they have acquired an understanding of the entire MIPS instruction set and the fundamentals of assembly language. Computer arithmetic, pipelining, and memory hierarchies are treated to the same evolutionary approach with worked examples and incremental drawings supporting each new level of sophistication. The design, performance, and significance of I/O systems is also discussed in depth, and an entire chapter is devoted to the emerging architectures of multiprocessor systems.

Table of Contents:
Computer Organization and Design, Second Edition Contents; Computer Organization and Design: The Hardware/Software Interface, Second Edition; by David A. Patterson and John L. Hennessy; Foreword; Worked Examples; Computer Organization and Design Online; Preface; 1 Computer Abstractions and Technology; 1.1 Introduction; 1.2 Below Your Program; 1.3 Under the Covers; 1.4 Integrated Circuits: Fueling Innovation; 1.5 Real Stuff: Manufacturing Pentium Chips; 1.6 Fallacies and Pitfalls; 1.8 Historical Perspective and Further Reading; 1.9 Key Terms; 1.10 Exercises; 2 The Role of Performance; 2.1 Introduction; 2.2 Measuring Performance; 2.3 Relating the Metrics; 2.4 Choosing Programs to Evaluate Performance; 2.5 Comparing and Summarizing Performance; 2.6 Real Stuff: The SPEC95 Benchmarks and Performance of Recent Processors; 2.7 Fallacies and Pitfalls; 2.8 Concluding Remarks; 2.9 Historical Perspective and Further Reading ; 2.10 Key Terms; 2.11 Exercises; 3 Instructions: Language of the Machine; 3.1 Introduction; 3.2 Operations of the Computer Hardware; 3.3 Operands of the Computer Hardware; 3.4 Representing Instructions in the Computer; 3.5 Instructions for Making Decisions; 3.6 Supporting Procedures in Computer Hardware; 3.7 Beyond Numbers; 3.8 Other Styles of MIPS Addressing; 3.9 Starting a Program; 3.10 An Example to Put It All Together; 3.11 Arrays versus Pointers; 3.12 Real Stuff: PowerPC and 80x86 Instructions; 3.13 Fallacies and Pitfalls; 3.14 Concluding Remarks; 3.15 Historical Perspective and Further Reading; 3.16 Key Terms; 3.17 Exercises; 4 Arithmetic for Computers; 4.1 Introduction; 4.2 Signed and Unsigned Numbers; 4.3 Addition and Subtraction; 4.4 Logical Operations; 4.5 Constructing an Arithmetic Logic Unit; 4.6 Multiplication; 4.7 Division; 4.8 Floating Point; 4.9 Real Stuff: Floating Point in the PowerPC and 80x86; 4.10 Fallacies and Pitfalls; 4.11 Concluding Remarks; 4.12 Historical Perspective and Further Reading; 4.13 Key Terms; 4.14 Exercises; 5 The Processor: Datapath and Control; 5.1 Introduction; 5.2 Building a Datapath; 5.3 A Simple Implementation Scheme; 5.4 A Multicycle Implementation; 5.5 Microprogramming: Simplifying Control Design; 5.6 Exceptions; 5.7 Real Stuff: The Pentium Pro Implementation; 5.8 Fallacies and Pitfalls; 5.9 Concluding Remarks; 5.10 Historical Perspective and Further Reading; 5.11 Key Terms; 5.12 Exercises; 6 Enhancing Performance with Pipelining; 6.1 an Overview of Pipelining; 6.2 A Pipelined Datapath; 6.3 Pipelined Control; 6.4 Data Hazards and Forwarding; 6.5 Data Hazards and Stalls; 6.6 Branch Hazards; 6.7 Exceptions; 6.8 Superscalar and Dynamic Pipelining; 6.9 Real Stuff: PowerPC 604 and Pentium Pro Pipelines; 6.10 Fallacies and Pitfalls; 6.11 Concluding Remarks; 6.12 Historical Perspective and Further Reading; 6.13 Key Terms; 6.14 Exercises; 7 Large and Fast: Exploiting Memory Hierarchy; 7.1 Introduction; 7.2 The Basics of Caches; 7.3 Measuring and Improving Cache Performance; 7.4 Virtual Memory; 7.5 A Common Framework for Memory Hierarchies; 7.6 Real Stuff: The Pentium Pro and PowerPC 604 Memory Hierarchies; 7.7 Fallacies and Pitfalls; 7.8 Concluding Remarks; 7.9 Historical Perspective and Further Reading; 7.10 Key Terms; 7.11 Exercises; 8 Interfacing Processors and Peripherals; 8.1 Introduction; 8.2 I/O Performance Measures: Some Examples from Disk and File Systems; 8.3 Types and Characteristics of I/O Devices; 8.4 Buses: Connecting I/O Devices to Processor and Memory; 8.5 Interfacing I/O Devices to the Memory, Processor, and Operating System; 8.6 Designing an I/O System; 8.7 Real Stuff: A Typical Desktop I/O System; 8.8 Fallacies and Pitfalls; 8.9 Concluding Remarks; 8.10 Historical Perspective and Further Reading; 8.11 Key Terms; 8.12 Exercises; 9 Multiprocessors; 9.1 Introduction; 9.2 Programming Multiprocessors; 9.3 Multiprocessors Connected by a Single Bus; 9.4 Multiprocessors Connected by a Network; 9.5 Clusters; 9.6 Network Topologies; 9.7 Real Stuff: Future Directions for Multiprocessors; 9.8 Fallacies and Pitfalls; 9.9 Concluding Remarks-Evolution versus Revolution in Computer Architecture; 9.10 Historical Perspective and Further Reading; 9.11 Key Terms; 9.12 Exercises; A Assemblers, Linkers, and the SPIM Simulator; A.1 Introduction; A.2 Assemblers; A.3 Linkers; A.4 Loading; A.5 Memory Usage; A.6 Procedure Call Convention; A.7 Exceptions and Interrupts; A.8 Input and Output; A.9 SPIM; A.10 MIPS R2000 Assembly Language; A.11 Concluding Remarks; A.12 Key Terms; A.13 Exercises; B The Basics of Logic Design; B.1 Introduction; B.2 Gates, Truth Tables, and Logic Equations; B.3 Combinational Logic; B.4 Clocks; B.5 Memory Elements; B.6 Finite State Machines; B.7 Timing Methodologies; B.8 Concluding Remarks; B.9 Key Terms; B.10 Exercises; C Mapping Control to Hardware; C.1 Introduction; C.2 Implementing Combinational Control Units; C.3 Implementing Finite State Machine Control; C.4 Implementing the Next-State Function with a Sequencer; C.5 Translating a Microprogram to Hardware; C.6 Concluding Remarks; C.7 Key Terms; C.8 Exercises; Glossary; Index

About the Author :
David A. Patterson was the first in his family to graduate from college (1969 A.B UCLA), and he enjoyed it so much that he didn't stop until a PhD, (1976 UCLA). After 4 years developing a wafer-scale computer at Hughes Aircraft, he joined U.C. Berkeley in 1977. He spent 1979 at DEC working on the VAX minicomputer. He and colleagues later developed the Reduced Instruction Set Computer (RISC). By joining forces with IBM's 801 and Stanford's MIPS projects, RISC became widespread. In 1984 Sun Microsystems recruited him to start the SPARC architecture. In 1987, Patterson and colleagues wondered if tried building dependable storage systems from the new PC disks. This led to the popular Redundant Array of Inexpensive Disks (RAID). He spent 1989 working on the CM-5 supercomputer. Patterson and colleagues later tried building a supercomputer using standard desktop computers and switches. The resulting Network of Workstations (NOW) project led to cluster technology used by many startups. He is now working on the Recovery Oriented Computing (ROC) project. In the past, he served as Chair of Berkeley's CS Division, Chair and CRA. He is currently serving on the IT advisory committee to the U.S. President and has just been elected President of the ACM. All this resulted in 150 papers, 5 books, and the following honors, some shared with friends: election to the National Academy of Engineering; from the University of California: Outstanding Alumnus Award (UCLA Computer Science Department), McEntyre Award for Excellence in Teaching (Berkeley Computer Science), Distinguished Teaching Award (Berkeley); from ACM: fellow, SIGMOD Test of Time Award, Karlstrom Outstanding Educator Award; from IEEE: fellow, Johnson Information Storage Award, Undergraduate Teaching Award, Mulligan Education Medal, and von Neumann Medal. John L. Hennessy is the president of Stanford University, where he has been a member of the faculty since 1977 in the departments of electrical engineering and computer science. Hennessy is a fellow of the IEEE and the ACM, a member of the National Academy of Engineering, the National Academy of Science, the American Academy of Arts and Sciences, and the Spanish Royal Academy of Engineering. He received the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and shared the John von Neumann award in 2000 with David Patterson. After completing the project in 1984, he took a one-year leave from the university to co-found MIPS Computer Systems, which developed one of the first commercial RISC microprocessors. After being acquired by Silicon Graphics in 1991, MIPS Technologies became an independent company in 1998, focusing on microprocessors for the embedded marketplace. As of 2004, over 300 million MIPS microprocessors have been shipped in devices ranging from video games and palmtop computers to laser printers and network switches. Hennessy's more recent research at Stanford focuses on the area of designing and exploiting multiprocessors. He helped lead the design of the DASH multiprocessor architecture, the first distributed shared-memory multiprocessors supporting cache coherency, and the basis for several commercial multiprocessor designs, including the Silicon Graphics Origin multiprocessors. Since becoming president of Stanford, revising and updating this text and the more advanced Computer Architecture: A Quantitative Approach has become a primary form of recreation and relaxation.

Review :
"o:This book trains the student with the concepts needed to lay a solid foundation for joining this exciting field. More importantly, this book provides a framework for thinking about computer organization and design that will enable the reader to continue the lifetime of learning necessary for staying at the forefront of this competitive discipline. —John Crawford, Intel Fellow, Director of Microprocessor Architecture, Intel