A Case Study of Cost Deduction in Multi-Site Testing for the Semiconductor Industry

With the increasing demand for high-complexity consumer Electronic products, the design of New Semiconductor chips needs to provide the required flexibility and speed. This trend shows that the functionality built into a single Semiconductor chip has continuously improved compared to the functionality 20 years ago. In contrast, Testing Costs in Semiconductor industries today can reach a substantial percent of the total Manufacturing Cost, thus affecting the Profit Margin. Numerous approaches have been introduced to lessen Testing Costs; one of them is the Multi-site Testing. Two case studies were conducted to determine the effectiveness of Multi-site Testing in reducing Testing Costs hence to improve the profit margin of the multi-sites test equipments. To achieve the research goal, a Multi-site test Cost Model and Profit Model were developed using the test Cost economic Model developed by Evan (1999) based on the economic theory of the firm, and by integrating important elements including economic Profit Margin and technology Multi-site efficiency. These models enabled the researcher to measure the capabilities of the Multi-site Testing for the Cost of Test Deduction and it effectiveness in relation to improving the Profit Margin. The case studies were conducted on two types of Test-equipment, namely, Wafer-Ring and Pick-and-Place Test-equipment setup. Five Multi-site configurations were configured on both Test-equipment setups for comparison. Testing time, Indexing time, and Test yield-data were collected for the purpose of establishing the Testing Cost and calculating the Profit Margin. Four hypotheses were tendered to analyze the performance of the Test-equipment setup, including Multi-site versus Multi-site efficiency, Multi-site versus Testing throughput, Multi-site versus Testing Cost and Multi-site versus Profit Margin improvement. The findings were analyzed using one-way ANOVA, Post-hoc test, and factorial ANOVA. This research established that increasing the number of test sites is not sufficient to guarantee reduced Testing Cost while maintaining Profit Margin because, once the number of test sites increases correspondingly, the Testing time will increase as well. It is therefore proposed that future work be conducted on the Multi-site Testing Approach together with other Testing Approaches that can reduce Testing time, such as concurrent Testing.

About the Author :
Khoo Voon Ching holds two Master's degrees, namely, the M.Sc by research from Asia e University and a Master of Business Administration degree from Akamai University, USA. Voon Ching obtained his professional qualifications as an incorporated engineer from the Engineering Council, UK, and as a certified planning engineer from the American Academy of Project Management, USA. He also studied in the University Technology of Malaysia to obtain his diploma in Mechanical Engineering and in Institute First Robotics Industrial Science to ac-quire an advanced diploma in Robotics and Automation Engineering. Voon Ching has many years of industry experience, specializing in automation and semiconductor testing. He first worked as a service engineer before he moved to Semiconductor Testing Automation. As a sales manager in semiconductor's test-industry, he was involved in multi-site test handler sales and service activities. He implemented multi-site testing handlers in many MNCs involved in semiconductor testing, which primarily aimed to reduce testing costs. His research interests include technology management, cost reduction through technology, and the efficiency of technology to improve human condition. Mr. Khoo is a member of the Institution of Mechanical Engineers and the International Associations of Engineers. He is a fellow of the American Academy of Project Management.