VLSI for Artificial Intelligence and Neural Networks

This book is an edited selection of the papers presented at the International Workshop on VLSI for Artifidal Intelligence and Neural Networks which was held at the University of Oxford in September 1990. Our thanks go to all the contributors and especially to the programme committee for all their hard work. Thanks are also due to the ACM-SIGARCH, the IEEE Computer Society, and the lEE for publicizing the event and to the University of Oxford and SUNY-Binghamton for their active support. We are particularly grateful to Anna Morris, Maureen Doherty and Laura Duffy for coping with the administrative problems. Jose Delgado-Frias Will Moore April 1991 vii PROLOGUE Artificial intelligence and neural network algorithms/computing have increased in complexity as well as in the number of applications. This in tum has posed a tremendous need for a larger computational power than can be provided by conventional scalar processors which are oriented towards numeric and data manipulations. Due to the artificial intelligence requirements (symbolic manipulation, knowledge representation, non-deterministic computations and dynamic resource allocation) and neural network computing approach (non-programming and learning), a different set of constraints and demands are imposed on the computer architectures for these applications.

Table of Contents:
1 Architecture and Hardware Support for AI Processing.- 1.1 VLSI Design of a 3-D Highly Parallel Message-Passing Architecture.- 1.2 Architectural Design of the Rewrite Rule Machine Ensemble.- 1.3 A Dataflow Architecture for AI.- 1.4 Incremental Garbage Collection Scheme in KL1 and Its Architectural Support of PIM.- 1.5 COLIBRI: A Coprocessor for LISP based on RISC.- 1.6 A CAM Based Architecture for Production System Matching.- 1.7 SIMD Parallelism for Symbol Mapping.- 1.8 Logic Flow in Active Data.- 1.9 Parallel Analogue Computation for Real-Time Path Planning.- 2 Machines for Prolog.- 2.1 An Extended Prolog Instruction Set for RISC Processors.- 2.2 A VLSI Engine for Structured Logic Programming.- 2.3 Performance Evaluation of a VLSI Associative Unifier in a WAM Based Environment.- 2.4 A Parallel Incremental Architecture for Prolog Program Execution.- 2.5 An Architectural Characterization of Prolog Execution.- 2.6 A Prolog Abstract Machine for Content-Addressable Memory.- 2.7 A Multi-Transputer Architecture for a Parallel Logic Machine.- 3 Analogue and Pulse Stream Neural Networks.- 3.1 Computational Capabilities of Biologically-Realistic Analog Processing Elements.- 3.2 Analog VLSI Models of Mean Field Networks.- 3.3 An Analogue Neuron Suitable for a Data Frame Architecture.- 3.4 Fully Cascadable Analogue Synapses Using Distributed Feedback.- 3.5 Results from Pulse-Stream VLSI Neural Network Devices.- 3.6 Working Analogue Pulse-Firing Neural Network Chips.- 3.7 Pulse-Firing VLSI Neural Circuits for Fast Image Pattern Recognition.- 3.8 An Analog Circuit with Digital I/O for Synchronous Boltzmann Machines.- 4 Digital Implementations of Neural Networks.- 4.1 The VLSI Implementation of the ? Architecture.- 4.2 A Cascadable VLSI Architecture for the Realization of LargeBinary Associative Networks.- 4.3 Digital VLSI Implementations of an Associative Memory Based on Neural Networks.- 4.4 Probabilistic Bit Stream Neural Chip: Implementation.- 4.5 Binary Neural Network with Delayed Synapses.- 4.6 Syntactic Neural Networks in VLSI.- 4.7 A New Architectural Approach to flexible Digital Neural Network Chip Systems.- 4.8 A VLSI Implementation of a Generic Systolic Synaptic Building Block for Neural Networks.- 4.9 A Learning Circuit That Operates by Discrete Means.- 4.10 A Compact and Fast Silicon Implementation for Layered Neural Nets.- 5 Arrays for Neural Networks.- 5.1 A Highly Parallel Digital Architecture for Neural Network Emulation.- 5.2 A Delay-Insensitive Neural Network Engine.- 5.3 A VLSI Implementation of Multi-Layered Neural Networks: 2-Performance.- 5.4 Efficient Implementation of Massive Neural Networks.- 5.5 Implementing Neural Networks with the Associative String Processor.- Contributors.