Design of Interconnection Networks for Programmable Logic

The complexity of digital logic systems has increased steadily and rapidly for the last several decades due to a steady trend in technology scaling. As current manufacturing technology reaches the deep-submicron level, more and more low-level design effort is required to create a working design. This presents a growing cost and productivity problem for digital systems, which are also tending to increase in complexity at the systems level. At the same time, the capabilities of programmable logic devices have been advancing as they have progressed from PALs to CPLDs and now to FPGAs. Modern-day FPGAs can implement entire digital systems. They are increasingly attractive to systems-level designers, but in many cases their performance is inadequate, or they contain insufficient memory, or they lack key intellectual property cores. Hence, there is a growing demand for merging programmable logic technology with custom deep-submicron VLSI technology. If there is one particular aspect of programmable logic that is not well understood, that consumes the most area, or that is responsible for the most delay, it is the interconnect. This volume presents the latest research results on the design of interconnect for programmable logic. The emphasis is on building the knowledge and tools for the automatic generation of interconnect structures. In this regard, the book presents design methodologies and applications for sparsely populated crossbars, clusters of lookup tables, switch blocks, and transistor-level routing switch design. It provides valuable information for both designers and architects about the area and delay implications of programmable interconnect. FPGA architects and System-on-Chip designers interested in exploring the integration of custom logic and programmable logic should find this work particularly useful.

Table of Contents:
1. Introduction.- 2. Interconnection Networks.- 3. Models, Methodology and CAD Tools.- 4. Sparse Crossbar Design.- 5. Sparse Cluster Design.- 6. Routing Switch Circuit Design.- 7. Switch Block Design.- 8. Conclusions.- Appendices.- A Switch Blocks: Reduced Flexibility.- A.1 Introduction.- A.4 Results.- A.5 Summary.- B Switch Blocks: Diverse Design Instances.- C VPRx: VPR Extensions.- C.1 Determination of Router Effort.- C.2 Routing Graph and Netlist Changes (Sparse Clusters).- C.3 Area and Delay Calculation Improvements.- C.4 Runtime Improvements.- C.5 Experimental Noise Reduction.- C.6 Correctness Changes.- References.