Elliptic Curve Cryptography: A Study and FPGA Implementation

This dissertation, "Elliptic Curve Cryptography: a Study and FPGA Implementation" by Chiu-wa, Ng, 吳潮華, was obtained from The University of Hong Kong (Pokfulam, Hong Kong) and is being sold pursuant to Creative Commons: Attribution 3.0 Hong Kong License. The content of this dissertation has not been altered in any way. We have altered the formatting in order to facilitate the ease of printing and reading of the dissertation. All rights not granted by the above license are retained by the author. Abstract: Abstract of thesis entitled "Elliptic Curve Cryptography - A Study and FPGA Implementation" Submitted by NG CHIU WA for the degree of Master of Philosophy at The University of Hong Kong in June 2004 Elliptic curve cryptography (ECC) is an attractive alternative to RSA for public key cryptographic applications, because it requires a much smaller key length than RSA for an equivalent level of security, and hence performs better in terms of processing load, memory and power requirements. ECC has been included in popular security standards such as IEEE P1363, and commercial products using ECC have started to appear. Hardware implementation of ECC is both more efficient and secure than software implementation. The objective of this study is to design efficient hardware components for ECC. In particular, it investigates the hardware implementation of three computationally intensive cryptographic operations: elliptic curve scalar multiplication, finite field division, and hash. Hardware architectures are developed and modeled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) and then implemented in Field Programmable Gate Array (FPGA). The performance of the designs is also analyzed. Five cryptographic components are developed in this study. A scalable elliptic curve processor based on an improved finite field multiplier is designed to support elliptic curve scalar multiplication of arbitrary bit lengths. To improve the performance of finite field division, a word-based scalable GF(2 ) divider which achieves a high level of parallelism is developed. A unified GF(p) and GF(2 ) divider operating in full bit length is implemented for high performance cryptographic applications such as ECDSA, in which the two division operations are required. Finally, using resource sharing architectures, hash processors for the MD5/RIPEMD-160 and the Whirlpool are designed and implemented. The unified architecture for MD5 and RIPEMD-160 is suitable for the current 160-bit ECC applications, while the 512-bit Whirlpool implementation would suit future applications which require larger key sizes. ii DOI: 10.5353/th_b2970633 Subjects: Cryptography Curves, Elliptic Field programmable gate arrays