Design Techniques for Ultra-Low-Voltage and Ultra-Low-Power Pipelined Adcs.

This thesis addresses two important aspects of pipelined analog-to-digital converter (ADC) design. The first one is regarding a pipelined ADC with ultra-low supply voltage. As CMOS technology advances, lower supply voltages are expected in the near future. We explore its design feasibility and implications. The second aspect is related to minimizing the total power consumption of the pipelined ADC. In particular the power associated with the reference voltage buffer is addressed. A 0.5V 8bit pipelined ADC operating at 10MS/ss is proposed. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and signal path sampling circuit. A 0.5V operational transconductance amplifier (OTA) is presented that provides interstage amplification with an 8bit performance for the pipelined ADC operating at 10MS/s. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4mW for 10MS/s operation at 0.5V supply voltage. Measured peak SNDR is 48.1 dB and peak SFDR is 57 2dB for a full-scale sinusoidal input. Maximal integral nonlinearity (INL) and differential nonlinearity (DNL) are 1.12LSB/- 1.19LSB and 0.55LSB/-0.48LSB, respectively. The prototype achieves a figure-of-merit (FOM) of 1.15pJ/Conv. Step. It was fabricated on a standard 90nm CMOS process and measures 1.2mm x 1.2mm. A low power stage architecture for a IV 8bit 100MS/s pipelined ADC using current-charge-pump multiplying digital-to-analog conversion (MDAC) circuit is presented. By avoiding the use of OTAs for the interstage amplification and eliminating power hungry buffers for the reference voltages, the proposed current-charge-pump pipelined ADC consumes much less power and thus achieves very high operation efficiency. Two versions of inverter based comparators are employed in the signal and sub-ADC paths. The design involves minimum analog circuitry and is digital dominant. It consumes 1.39mW for 100MS/s operation at 1V supply voltage. Measured peak SNDR and SFDR are 37.1dB and 46.7dB respectively, with a -1dBFS sinusoidal input at Nyquist frequency. Maximum INL and DNL are 2LSB/-2.3LSB and 1LSB/-0.8LSB, respectively. This concept-proving prototype achieves an FOM of 2370/Conv. Step while largely alleviating the requirement of reference voltage buffers. The core circuit occupies 0.044mm2. The design was fabricated on a standard 90nm CMOS process using regular V T devices.