Towards an Adaptive Interconnect for System-On-Chip.

Emerging System-on-Chip (SoC) platforms, such as those for mobile systems, are typically battery-powered systems that have to support a wide range of streaming applications such as video and audio. To meet the high performance requirements for these systems, SoCs integrate various hardware resources such as CPUs, DSPs, Memory and I/O peripherals. These hardware resources normally communicate using a shared medium such as the bus system. For large SoCs, the bus-based schemes become restrictive because they are non-scalable and have higher overheads that adversely impact performance and energy consumption. Network-on-Chip (NoC) architectures were therefore proposed to solve the scalability problem experienced in bus-based SoCs. They incorporate a communication infrastructure defined by a network topology, routers and switches, in order to provide a scalable and high performance interconnection between SoC resources while satisfying the constraints of embedded platforms. This work: (1) conducts a comprehensive empirical and analytical study to characterize the impact of NoC topology on performance, as well as energy and area requirements; (2) introduces the concept of Field Adaptable NoC (FAN); and (3) proposes the use of Network Calculus as a NoC modeling technique for design space exploration. The empirical study aimed at exploring different configurations of network on chip has been conducted. Different topologies are selected and analyzed using specific routing and switching methods to check the suitability for NoC. Additionally, since the energy and area are the primary concerns in NoC, models for energy and area are adapted and simulators are built to calculate these metrics. The static on-chip interconnects, despite their advantages over bus based systems, have latency and throughput that depend on the topology as well as application traffic scenarios. Application-specific optimizations, needed to address this issue, require an adaptable NoC infrastructure to allow in-field customizations. A methodology for augmenting a NoC with a programmable infrastructure that allows application-specific adaptation called Field Adaptable NoC (FAN) is presented. The resulting infrastructure provides the flexibility required to maximize the performance for a given application, while adhering to the system constraints such as energy and area. To evaluate the proposed methodology of the adaptable NoC, the WK-recursive on-chip interconnect as well as the 2D Mesh network are used as case studies. Performance analysis and evaluation of on-chip interconnect (OCI) architectures are widely based on system level simulation techniques. Due to the time-consuming nature of simulation based approaches, as well as their limitations in providing an understanding on the effects of various design parameters, analytical models for NoCs are essential. Therefore, we introduce Network Calculus for design space exploration and as a suitable analytical modeling tool for estimating and evaluating the performance of on-chip interconnects. One of the primary advantages of Network Calculus is its ability to model network traffic and service in terms of bounds, which enables worst-case analyses to be carried out. To validate this analytical method and demonstrate its applicability for NoC, different scenarios for application traffic are analyzed for different NoC configurations and compared with simulation. The results from the analyses closely match those obtained from the comprehensive empirical study.