The Effect of an Imposed Current on the Creep of Tin Silver Copper Interconnects

There has been substantial work done on the properties of solder interconnects due to the global transition to lead free electronics. These interconnects create an electrical connection, which current will pass through for much of the interconnects' lifespan. As such, it is imperative in the testing of any solder alloy to examine the mechanical, thermal, and microstructural behavior of the interconnect while it is under an imposed current. The imposed current drives several internal effects that may impact the behavior of the interconnect; creating a complicated state within the interconnect. This thesis is the first study of the couple between current and mechanical properties of these interconnects. Idealized SnAgCu interconnects were made consisting of double-shear specimens that contained paired solder joints, 400x400mum in cross-section, 200mum in thickness on a Cu substrate. Different representative microstructures were prepared by pre-treating the interconnects via electromigration and isothermal aging. Samples were tested with and without an imposed current, and at a variety of temperatures. These tests consistently yielded two unexpected results. First, the relative increase in creep rate, for a given imposed current, is nearly the same over a range of temperatures and starting microstructures. Second, when tests are done at equivalent temperatures (to compensate for Joule heating) the creep rate is lower when under an imposed current than under isothermal conditions. To explain this phenomena, internal gradients within the interconnects were investigated. The temperature profile was shown to be constant at a given current density. Given constant temperature, and a microstructure that includes interfacial voids, the effect of the imposed current on the vacancy concentration was examined. It was found that the current depletes the joint of vacancies, lowering the average creep rate, and introducing observable heterogeneities in the creep pattern. This result was also found to be dependant on the specific locations of the voids, which act as vacancy sources or sinks. The usual Dom equation then provides a very useful basis for evaluating the change of creep rate with current. Actual microelectronic devices were also examined under an imposed current. Due to the complex geometry and composition of the samples, lower current densities were necessitated. As such, current induced effects were lessened, yet comparisons show similar behavior to the idealized interconnects. Our idealized model was applied to these devices, and yielded activation energies consistent with previous data. Finally, lifetime reliability projections were made for use in the future design of lead free microelectronic devices.