Charge Trapping Study of Hafnium-Based Gate Dielectrics for Advanced CMOS Technology

In order to reduce the large gate leakage current when scaling SiO 2 to its fundamental limit, high-kappa gate dielectrics need to be used in advanced CMOS technology. Among all the high-kappa candidates, hafnium-based gate dielectrics have been widely accepted for the 45-32nm technology node and beyond. This dissertation research deals with the charge trapping induced threshold voltage instability in the hafnium oxide gated MOSFETs. Various characterization methodologies are used in the charge trapping study. SMU Pulsed I-V and an automated measurement program are implemented into the traditional electrical stress experiment. New techniques, including Pulsed I-V, PASHEI, and On-the-Fly methods, are demonstrated in order to capture the fast trapping effect, and minimize the recovery of trapped charge in high-kappa gated MOSFETs. The charge trapping properties in HfO2 gated MOSFETs are investigated. The following observations have been recorded: (1) large improvement in trapping-induced instability can be realized by replacing poly-Si gates with metal gates; (2) charge trapping at existing bulk traps is the major contributor of the threshold voltage shifts; (3) electron traps have shallower energy levels in the bandgap than hole traps; (4) gate current components (i.e., electron or hole current) play an important role in the net trapping effect. An extensive experimental study of the effective capture cross-sections of electron traps in ultra-thin high-kappa gate dielectrics is conducted. The strong dependence of the capture cross-section on the gate leakage current is revealed for the first time. Numerous possibilities have been investigated to understand the unusually low values of the extracted capture cross-sections in ultra-thin high-kappa gate dielectrics, and it is concluded that they are primarily due to the fact that the injection currents used to study the trapping effects are mainly due to the direct tunneling mechanism, which suffers from very little scattering, and leads to very small trapping probability. The omission of the detrapping effect in the 1st order trapping model also contributes to some extent. Combining high mobility channels with high-kappa gate dielectrics is a promising approach for the development of future CMOS technology. In this dissertation, the interface between Hf-based gate dielectrics and the SiGe channel is characterized by the charge pumping technique. An abnormal charge pumping current component has been discovered, and attributed to the SiGe/Si hetero-junction interface. The interface-trap density is extracted by properly taking into account this abnormal current component.