A Physics-Based Design Methodology for Digital Systems Robust to Esd-CDM Events

This work is motivated by two technology trends which are seemingly irreconcilable. On one hand, continued aggressive scaling of CMOS has major negative implications for both device-level and system-level reliability. On the other hand, market forces demand that high-volume integrated circuits (IC) manufacturing be extremely cost-effective. Both of these trends work to make reliability difficult. To reconcile these trends, design choices need to be better informed and guided by physical understanding. In this work, a physics-based view of device behavior is demonstrated that improves system-level reliability. Two examples discussed in this work relate Electro-Static Discharge (ESD) and Early Life Failure (ELF)---leading causes of chip failure. A general view of reliability is first presented. Experiments are used to study the behavior of failing transistors; this understanding enables the development of design techniques that include online circuit failure prediction and burn-in reduction. The development of a physics-based post-breakdown transistor macro-model is presented. A design methodology and protection strategy for digital systems, robust to ESD-CDM events, is developed and validated for commercial 90 nm and 130 nm MOS technologies. The resulting simulation approach correctly predicts the location of core transistors, in a complex System-on-Chip environment, that can be broken down by external ESD-CDM events. A scalable post-breakdown transistor macro-model is developed for reliability simulations and validated for both 90 nm and 130 nm technologies. This macro-model has been shown to be accurate to within 10% for 30 different MOS device types and geometries. An Ultra-Fast Transmission Line Pulsing system (UFTLP) has been demonstrated to be capable of producing pulses with 40 ps pulse widths. This capability enables the investigation and characterization of gate oxide reliability down to the sub-100 ps regime; by contrast prior reports for gate oxide reliability studies have been limited to the nanosecond regime in resolving breakdown events. Using these measurement, modeling and simulation techniques, the design methodology and protection strategy was successfully implemented into a commercial mainstream design flow. Specific IC test chips, designed using conventional ESD rules targeted for 500 V ESD-CDM stress protection, were used as test vehicles for the new methodology; resulting design changes resulted in chips that passed 750 V levels of ESD-CDM stress, reaching the highest level of stress testing on JEDEC-compliant equipment.