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Architectural Explorations for High-Performance Field-Programmable Gate Arrays

Architectural Explorations for High-Performance Field-Programmable Gate Arrays


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About the Book

Cell-based design technology has dominated ASIC implementation over the past quarter century by offering an economically compelling combination of low manufacturing cost and acceptable design and prototyping costs. With the advent of sub-100nm CMOS technologies, the design and prototyping costs of cell-based implementation have become prohibitive for most ASICs, making FPGAs increasingly popular. Current FPGAs, however, cannot meet the performance requirements of many ASICs due to their high programming overhead. Therefore, designing high-performance FPGA architecture is becoming increasingly important. This thesis presents several architecture studies aimed at improving FPGA performance. We first present our work on performance benefits of monolithically stacked 3D-FPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and interconnects, are investigated. A Virtex-II style 2D-FPGA fabric is used as a baseline architecture to quantify the relative improvements in logic density, delay, and power consumption achieved by such a 3D-FPGA. It is assumed that only the switch-transistor and configuration memory cells can be moved to the top layers and that the 3D-FPGA employs the same logic block and programmable interconnect architecture as the baseline 2D-FPGA. Assuming a configuration memory cell that is


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Product Details
  • ISBN-13: 9781243560575
  • Publisher: Proquest, Umi Dissertation Publishing
  • Publisher Imprint: Proquest, Umi Dissertation Publishing
  • Height: 246 mm
  • Weight: 249 gr
  • ISBN-10: 1243560576
  • Publisher Date: 01 Sep 2011
  • Binding: Paperback
  • Spine Width: 7 mm
  • Width: 189 mm


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