Lithography-Driven Design for Manufacturing in Nanometer-Era VLSI

Photolithography has been a key enabler of the aggressive IC technology scaling implicit in Moore's Law. As minimum feature sizes approach the physical limits of lithography and the manufacturing process, resolution enhancement techniques (RETs) dictate certain tradeoffs with various aspects of process and performance. This in turn has led to unpredictable design, unpredictable manufacturing, and low yield. As a result, close communication between designer and manufacturer has become essential to overcome the uncertainties of design and manufacturing. The design for manufacturability (DFM) paradigm has emerged recently to improve communications at the design-manufacturing interface and to reduce manufacturing variability. DFM is a set of technologies and methodologies that both help the designer extract maximum value from silicon process technology and solve "unsolvable" manufacturing challenges. Traditional DFM techniques, which include design rule check (DRC) and optical proximity correction (OPC), have been successfully used until now. However, as the extent and complexity of lithography variations increase, traditional techniques are no longer adequate to accommodate the various lithography demands. This thesis focuses on ways to mitigate the impact of lithography variations on design by establishing new interfaces between design and manufacturing. The motivations for doing so are improved printability, timing and leakage as well as reduced design cost. To improve printability, we propose a detailed placement perturbation technique for improved depth of focus and process window. Using a dynamic programming (DP)-based method for the perturbation, the technique facilitates insertion of scattering bars and etch dummy features, reducing inter-cell forbidden pitches almost completely. We also propose a novel auxiliary pattern-enabled cell-based OPC which can improve the edge placement error over cell-based OPC. The technique improves runtime which has grown unacceptably in model-based OPC, while retaining its runtime advantage as well as timing and leakage optimization. The detailed placement framework is also available to allow opportunistic insertion of auxiliary pattern around cell instances in the design layout. Aberration leads to linewidth variation which is fundamental to achieve timing performance and manufacturing yield. We describe an aberration-aware timing analysis flow that accounts for aberration-induced cell delay variations. We then propose an aberration-aware timing-driven global placement technique which utilizes the predictable slow and fast regions created on the chip due to aberration to improve cycle time. The use of the technique along with field blading achieves significant cycle time improvement. DoseMapper technique adopted in advanced lithography equipments has been used to reduce the across-chip linewidth variation. We propose a novel method to enhance timing yield as well as reduce leakage power by combined dose map and placement optimizations. The new dose map is not determined to have the same critical dimension (CD) in all transistor gates, but optimized to have different linewidths. That is, for devices on setup timing-critical paths, a smaller than nominal CD will be desirable, since this creates a faster-switching transistor. On the other hand, for devices on hold timing-critical paths, a larger than nominal gate CD will be desirable since this creates a less leaky transistor. Last, the golden verification signoff tool using simulation-based approach represents a runtime-quality tradeoff that is high in quality, but also high in runtime. We are motivated to develop a low-runtime pre-filter that...