Hardware Implementation of a Synchronization State Buffer in VHDL.

Current trends in microprocessor chips are heading towards multi-core architectures. This new architecture utilizes multiple processors on a chip instead of using a single powerful processor. This allows for increased parallelism which can lead to improved performance. With this trend, new challenges occur and must be addressed. With multiple processors, it becomes possible for a shared memory location to be addressed at the same time by multiple processing units. Memory synchronization is one challenge that needs to be handled when working with shared memory in a multi-core configuration. If one of these units attempts to operate on a block of data, it can create a data hazard depending on when the operation occurs. This is handled by utilizing fine-grain synchronization. Fine-grain synchronization is very important in utilizing the computational power of multi-core processors. However, it can be difficult due to overhead, storage cost, scalability, and the level of granularity that is applicable in the situation. One proposed solution to this challenge is the Synchronization State Buffer (SSB) proposed by Weirong Zhu in his recent Ph.D. thesis at the University of Delaware. The SSB was developed on the Cyclops-64 supercomputer architecture using a simulation program created by Weirong. The SSB is a unit that can be run alongside the memory controller and handle synchronization requests without the overhead necessary for other methods such as memory tagging. One important observation of Weirong's work was that only a small amount of the memory is being synchronized at one given time, therefore a buffer that is a small fraction of the size of the entire memory is all that is needed. This buffer holds the states of locations in the memory based on what information it receives from the memory controller. The SSB has been shown to function effectively in software simulations and the results can be found in the Weirong's work. The standing questions regarding the SSB are as follows: Can a SSB hardware solution be feasible to implement in a real system? Is it small and fast enough to avoid interference with other operations in the system? Finally, does it operate as expected in hardware? While all other testing had been done in software, it is now possible to answer these questions through the work done in this thesis. The main contributions of this thesis are as follows: A. A hardware design was proposed and created based on the original design from Weirong Zhu. A working VHDL design was created using the Xilinx ISE tools. The implementation was designed using the Cyclops-64 on-chip SRAM specifications found in the Principles of Operations and the previous work done with the SSB. The design has been shown to be a feasible solution to be implemented in hardware. B. The design took into account the size of the device, and efforts were made to make the device fairly small in order to save valuable chip space. It has been shown that the device is small enough to work smoothly with the SRAM controller on the chip. C. Tests have been performed on the design that provide correct results. An experimental platform was created to verify the proposed SSB hardware design. The experimentations performed present a wide range of tests to ensure the device functions properly. The results have shown that the hardware design operates in less than 2 cycles, therefore not interfering with other system processes. This thesis will discuss the proposed hardware design by describing its features, its creation, and its testing. The thesis intends to provide the reader with a description of the SSB that has been shown to operate according to the original design.