About the Book
Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. Pages: 81. Chapters: Microcode, Instruction set, Itanium, Very long instruction word, Control store, Memory barrier, GPGPU, Branch predictor, Microarchitecture, Classic RISC pipeline, Instruction pipeline, Burroughs large systems instruction sets, List of instruction sets, Berkeley RISC, Transport triggered architecture, MikroSim, Jazelle, Multithreading, Hazard, Out-of-order execution, Orthogonal instruction set, MIL-STD-1750A, TriMedia, Instruction cycle, Explicitly parallel instruction computing, Speculative multithreading, Register window, Branch predication, Speculative execution, Runahead, Delay slot, Tomasulo algorithm, Scoreboarding, Instruction-level parallelism, Prefetch input queue, XCore XS1-G4, DLX, ST200 family, XCore XS1-L1, Barrel processor, Interlock, Zero instruction set computer, Micro-operation, CEVA, Inc., Instruction prefetch, Instructions per cycle, Cycles per instruction, Memory-level parallelism, HOWTO article, Hardware scout, Reservation stations, Branch target predictor, MIPS-X, Decoupled architecture, Instruction window, Anticiparallelism, Minimal instruction set computer, Slipstream, Application-specific instruction-set processor, Instruction set matrix, Model-specific register, Reset vector, Branch misprediction, Unicore, Degree of parallelism, Bubble, Native mode, Re-order buffer, Operand forwarding, RH1750. Excerpt: Itanium ( ) is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel markets the processors for enterprise servers and high-performance computing systems. The architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. The Itanium architecture is based on explicit instruction-level parallelism, in which the compiler decides which instructions to execute in parallel. This contrasts with other s...
