About the Book
Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. Pages: 88. Chapters: Boolean satisfiability problem, Digital electronics, Ladder logic, Systems design, Netlist, Schematic, Electromigration, Signal integrity, Potential applications of carbon nanotubes, Programmable Array Logic, Standard cell, Technology CAD, Design For Test, Ultra-Large-Scale Systems, Satisfiability Modulo Theories, Semiconductor device modeling, Semiconductor process simulation, Power gating, Physical design, Design closure, Power network design, Network On Chip, Routing, High-level synthesis, Power optimization, Electromagnetic field solver, Logic simulation, Rent's rule, EDA database, Logic synthesis, And-inverter graph, Electronic circuit simulation, Asynchronous system, Simulation software, Schematic capture, Placement, Antenna effect, Semiconductor intellectual property core, Signoff, Hardware obfuscation, Substrate coupling, Engineering Change Order, Place and route, Input Output Buffer Information Specification, Register transfer level, Algorithmic State Machine, Design for manufacturability, Resolution enhancement technologies, Test compression, Graphical system design, IEC 61131-3, Design flow, Silicon compiler, Transaction-level modeling, Channel router, Logic optimization, Circuit extraction, Touchstone file, Electronic system level, Fault coverage, Elmore delay, Floorplan, HLV, Programmable logic array, Schematic editor, Black's equation, Multi-channel length, Multi-project wafer service, Noise margin, PBIST, Lee algorithm, IC layout editor, Symbolic simulation, State logic, Programmable system device, Universal Verification Methodology, Mask data preparation, Floorplanning, Maze runner, Generic array logic, Stuck-at fault, Dolphin Integration, Platform-based design, Fiduccia-Mattheyses algorithm. Excerpt: Digital electronics represent signals by discrete bands of analog levels, rather than by a continuou...
