About the Book
This book exhibits a unique way of explaining nanomaterials and devices and analyzing their design parameters to meet the sub-nanoregime challenges for low-power chip design. Since process variability, device sizing, and power supply scaling are ongoing challenges in very large-scale integration (VLSI) circuit designs, this book highlights the conventional and novel nanomaterials, devices and circuits, leakage current mitigation techniques, and other important trade-offs along with exhaustive analysis. More focus has been placed throughout the book on various trade-offs for high-speed and low-power VLSI devices and circuits co-design.
This book:
Discusses advanced nano-semiconductor devices such as FinFET, nanowires, tunnel field-effect transistors, carbon nanotube field-effect transistors, and high-electron-mobility transistors
Presents high-performance semiconductor devices at nanoscale technology nodes for the analysis of quantum effects and their impact on circuits and systems
Covers power dissipation and reduction techniques for high-performance devices
Explains both silicon and non-silicon devices for various applications like digital logic and analog/radio frequency applications
Examines the difficulties and practical design approaches for extremely low-power analog-integrated circuits
It is primarily written for senior undergraduates, graduate students, and academic researchers in the fields of electrical engineering, electronics and communications engineering, materials science, nanoscience, and nanotechnology.
Table of Contents:
1. Design and Analysis of Advance MOSFET. 2. FinFET and Its Application. 3. Future Directions and Roadmap for Nanoelectronics. 4. Analysis of HEMT and Its Applications. 5. Characterizations and applications of pomegranate synthesized biogenic silver nanoparticles. 6. Comparative analysis of 6T SRAM & ROM cell using CMOS technology at 200nm, 45nm and 7n. 7. FEFET in Computing Memory. 8. Advancements and Implications of Bioplastic Development: From Material Synthesis to Environmental Impact. 9. Variability in Tunnel Field Effect Transistor. 10. Enhancing 5G Network Connectivity with Fractal-Inspired 5-Port MIMO Antenna: Material-Based Analysis for Satellite Communication Systems. 11. 2D Nanomaterials Based THz Electromagnetic Radiators. 12. Nano Materials for Smiconductor Devices. 13. Design of MUX-Based CMOS 8-Bit Encoder Device for High-Speed 5G Flash ADC Binary Conversion in UWB Applications.
About the Author :
Balwinder Raj (MIEEE’2006) is currently working as Associate Professor at the National Institute of Technology Jalandhar, India. He has more than 15 years of teaching and research experience. He did BTech in Electronics Engineering (PTU Jalandhar), MTech in Microelectronics (PU Chandigarh), and PhD in VLSI Design (IIT Roorkee), India, in 2004, 2006, and 2010, respectively. For further research work, the European Commission awarded him the “Erasmus Mundus” Mobility of Life research fellowship for postdoc research work at the University of Rome, Tor Vergata, Italy, in 2010–2011. Dr Raj received India4EU (India for European Commission) Fellowship and worked as visiting researcher at KTH University, Stockholm, Sweden, October–November 2013. He also visited Aalto University in Finland as visiting researcher during June 2017.
He had received Best Teacher Award from the Indian Society for Technical Education (ISTE), New Delhi, in 26 July 2013. Dr Raj received the Young Scientist Award from the Punjab Academy of Sciences during 18th Punjab Science Congress held on 9 February 2015. He has also received research paper award in the International Conference on Electrical and Electronics Engineering held at Pattaya, Thailand, from 11 to 12 July 2015. Dr Raj has authored/co-authored 8 books, 15 book chapters, and more than 150 research papers in peer-reviewed international/national journals and conferences. His areas of interest in research are classical/non-classical nanoscale semiconductor device modeling; nanoelectronics and their applications in hardware security; sensors and circuit design; FinFET-based memory design; low-power VLSI design; digital/analog VLSI design; and FPGA implementation.
Suman Lata Tripathi is working as Professor in Lovely Professional University with more than 21 years of experience in academics and research. She has completed her PhD in the area of microelectronics and VLSI design from MNNIT, Allahabad, India. She did her MTech in Electronics Engineering from UP Technical University, Lucknow, and BTech in Electrical Engineering from Purvanchal University, Jaunpur, India. She is also a remote post-doc researcher at Nottingham Trent University, London, UK, in the year 2022. She has published more than 102 research papers in refereed Springer, Elsevier, IEEE, and IOP science journals; conference proceeding; and e-books. She has also published 13 Indian patents and 4 copyrights. She has guided four PhD scholars and four are under submission stage. She has organized several workshops, summer internships, and expert lectures for students. She has worked as a session chair, conference steering committee member, editorial board member, and peer reviewer in international/national IEEE, Springer, Wiley, etc., journal and conferences. She has received the “Research Excellence Award” in 2019 and “Research Appreciation Award” in 2020 and 2021 at Lovely Professional University, India. She is recipient of IGEN Women’s for Green Technology “Women’s Achievers Award” on International Women’s Day, 8 March 2023. She had received the best paper at IEEE ICICS-2018. She has also received funded project from SERB DST under the scheme TARE in the area of microelectronic devices. She has edited and authored more than 19 books in different areas of Electronics and Electrical Engineering. She is associated for editing work with top publishers like Elsevier, CRC Taylor and Francis, Wiley-IEEE, SP Wiley, Nova Science, and Apple Academic Press. She is also working as book series editor for title, “Smart Engineering Systems” CRC Press, “Engineering System Design for Sustainable Developments”, and “Decentralized Systems & Next Generation Internet” Wiley-Scrivener, and conference series editor for “Conference Proceedings Series on Intelligent Systems for Engineering Designs” CRC Press Taylor & Francis. She is serving as academic editor of Journal of Electrical and Computer Engineering (Scopus/WoS, Q2), International Journal of Reconfigurable Computing (Scopus, Q3), and Active and Passive Electronic Component (Scopus, Q4), Hindawi. She is associated as senior member IEEE, Fellow IETE, and Life member ISC and is continuously involved in different professional activities along with academic work. Her area of expertise includes microelectronics device modeling and characterization, low-power VLSI circuit design, VLSI design of testing, and advanced FET design for IoT, embedded system design, reconfigurable architecture with FPGAs, and biomedical applications.
Tarun Chaudhary did her BTech in Electronics and Communication Engineering from UIET, Panjab University, Chandigarh, in 2010; MTech. in VDAT (ECE) from NIT Hamirpur, Himachal Pradesh, in 2012; and PhD from NIT Hamirpur, Himanchal Pradesh, India, in the year 2017. During her PhD she has worked on the designing and mathematical modeling of vertical FET. She is currently working as Assistant Professor in ECE Department, Dr B R Ambedkar National Institute of Technology Jalandhar, India. She has worked as a faculty member under SMDP C2SD Project from October 2017 till November 2019. She is guiding PhD and PG scholars in the areas of nanoscale devices and circuits, and FPGAbased design. She has 5 book chapters and more than 25 research papers in peer-reviewed international/national journals and conferences. She has organized several STCs and workshops in the domain of VLSI design. Of the three students who are pursuing their PhD under her supervision, all are working on TFETs, NCFETs, and nanowire-based sensors. Her present research is largely focused on the design and modeling of nanoscale devices, TFETs, junctionless devices, and low-power VLSI design circuits.
Mandeep Singh has done his BTech in Electronics and Communication Engineering, MTech ECE (VLSI DESIGN) from Punjabi University, Patiala, and PhD from NIT Jalandhar, Punjab, India. He has eight-year teaching experience to teach undergraduate and master students in Punjab Technical University, India; the National Institute of Technology Uttarakhand, India; and Chaudhary Charan Singh University, Meerut, UP, India. Currently he is working as Postdoc Researcher in the Indian Institute of Technology Kanpur, UP, India. He has published various research papers in the domain of VLSI design and circuit. His areas of research are semiconductor device modeling, memory designs, CNT and nanowires, and low-power VLSI designs.
