Algorithmic and Knowledge-based CAD for VLSI: (Materials, Circuits and Devices)

The continuing growth in the size and complexity of VLSI devices requires a parallel development of well-designed, efficient CAD tools. Such tools must be available for the whole design cycle - synthesis and functional verification, testability analysis, test generation and fault coverage and layout. The majority of commercially available tools are based on an algorithmic approach to the problem and there is a continuing research effort aimed at improving existing tools of this form and developing new algorithms. The sheer complexity of the problem has, however, led to an interest in examining the applicability of expert systems and other knowledge based techniques to certain problems in the area and a number of results are becoming available. The aim of this book, which is based on material given at an IEE Colloquium of the same name, is to sample the present state-of-the-art in CAD for VLSI. It covers both newly developed algorithms and applications of techniques from the artificial intelligence community. The editors believe it will prove of interest to all engineers concerned with design and testing of integrated circuits and systems. Although it is not intended as a course text, many of the chapters will provide background reading for postgraduate and final year undergraduate students following courses in VLSI design. Chapters are arranged in three groups covering topics in synthesis, test and testability and layout.

Table of Contents:
Chapter 1: Expert assistance in digital circuit design Chapter 2: Use of a theorem prover for transformational synthesis Chapter 3: An overview of high level synthesis technologies for digital ASICs Chapter 4: Simulated annealing based synthesis of fast discrete cosine transform blocks Chapter 5: Knowledge based expert systems in testing and design for testability - an overview Chapter 6: Knowledge based test strategy planning Chapter 7: HIT: a hierarchical integrated test methodology Chapter 8: Use of fault augmented functions for automatic test pattern generation Chapter 9: Macro-test: a VLSI testable-design technique Chapter 10: An expert systems approach to analogue VLSI layout Chapter 11: Guaranteeing optimality in a gridless router using AI techniques

About the Author :
Gaynor Taylor is Professor of Systems Design and currently Head of the Department of Electronic Engineering at the University of Hull. She has been a member of the academic staff of the university since 1980 and is involved in teaching courses on CAD for VLSI and research into test pattern generation and design for testability for both digital and mixed analogue and digital devices. Prior to joining the university she spent a number of years at the GEC-Marconi Research Laboratories at Great Baddow where she was involved in the development of GAD tools for digital circuits and for passive filters. She received her BSc, MSc and PhD degrees from UMIST and is a Chartered Engineer and Fellow of the IEE. Gordon Russell has been on the academic staff of the Department of Electrical and Electronic Engineering at the University of Newcastle upon Tyne since 1979, where he has been involved in teaching and research into CAD tools for VLSI circuit design and design for testability techniques. He has also been involved in a number of SERC and DTI funded research projects in these areas. Before joining Newcastle University he spent five years at Edinburgh University, involved in a range of CAD activities, first in the Department of Computer Science, then in the Department of Electrical Engineering and finally in the Wolfson Microelectronics Institute. He is coauthor/coeditor of five books related to testing and other aspects of CAD for VLSI and has given a number of invited lectures at universities throughout Europe on the application of expert systems to test pattern generation and design for testability. He is a Chartered Engineer and a member of the IEE and IEEE. He received his BSc and PhD degrees from the University of Strathclyde.