Hot-Carrier Reliability of MOS VLSI Circuits: (227 The Springer International Series in Engineering and Computer Science)

This volume addresses the issues related to hot-carrier reliability of MOS VLSI circuits, ranging from device physics to circuit design guidelines. It presents a unified view of the physical mechanisms involved in hot-carrier induced device degradation, the prevalent models for these mechanisms, and simulation methods for estimating hot-carrier effects in the circuit environment. The newly emerging approaches to the VLSI design-for-reliability and rule-based reliability diagnosis are also discussed in detail. Hot-Carrier Reliability of MOS VLSI Circuits is primarily for use by engineers and scientists who study device and circuit-level reliability in VLSI systems and develop practical reliability measures and models. VLSI designers will benefit from this book since it offers a comprehensive overview of the interacting mechanisms that influence hot-carrier reliability, and also provides useful guidelines for reliable VLSI design. This volume can be used as an advanced textbook or reference for a graduate-level course on VLSI reliability.

Table of Contents:
1. Introduction.- 1.1. The Concept of IC Reliability.- 1.2. Design-for-Reliability.- 1.3. VLSI Reliability Problems.- 1.4. Gradual Degradation versus Catastrophic Failures.- 1.5. Hot-Carrier Effects.- 1.6. Overview of the Book.- References.- 2. Oxide Degradation Mechanisms in Mos Transistors.- 2.1. Introduction.- 2.2. MOS Transistor: A Qualitative View.- 2.3. The Nature of Gate Oxide Damage in MOSFETs.- 2.4. Injection of Hot Carriers into Gate Oxide.- 2.5. Oxide Traps and Charge Trapping.- 2.6. Interface Trap Generation.- 2.7. Bias Dependence of Degradation Mechanisms.- 2.8. Degradation under Dynamic Operating Conditions.- 2.9. Effects of Hot-Carrier Damage on Device Characteristics.- 2.10. Hot-Carrier Induced Degradation of pMOS Transistors.- References.- 3.Modeling of Degradation Mechanisms.- 3.1. Preliminary Remarks.- 3.2. Quasi-Elastic Scattering Current Model.- 3.3. Charge (Electron) Trapping Model.- 3.4. Impact Ionization Current Model.- 3.5. Interface Trap Generation Model.- 3.6. Trap Generation under Dynamic Operating Conditions.- References.- 4. Modeling of Damaged Mosfets.- 4.1. Introduction.- 4.2. Representation of Hot-Carrier Induced Oxide Damage.- 4.3. Two-Dimensional Modeling of Damaged MOSFETs.- 4.4. Empirical One-Dimensional Modeling.- 4.5. An Analytical Damaged MOSFET Model.- 4.6. Consideration of Channel Velocity Limitations.- 4.7. Pseudo Two-Dimensional Modeling of Damaged MOSFETs.- 4.8. Table-Based Modeling Approaches.- References.- 5. Transistor-Level Simulation for Circuit Reliability.- 5.1. Introduction.- 5.2. Review of Circuit Reliability Simulation Tools.- 5.3. Circuit Reliability Simulation Using iSMILE: A Case Study.- 5.4. Circuit Simulation Examples.- 5.5. Evaluation of the Simulation Algorithm.- 5.6. Identification of Critical Devices.- References.- 6. Fast Timing Simulation for Circuit Reliability.- 6.1. Introduction.- 6.2. ILLIADS-R: A Fast Timing and Reliability Simulator.- 6.3. Fast Dynamic Reliability Simulation.- 6.4. Circuit Simulation Examples with ILLIADS-R.- 6.5. iDSIM2: Hierarchical Circuit Reliability Simulation.- References.- 7. Macromodeling of Hot-Carrier Induced Degradation in Mos Circuits.- 7.1. Introduction.- 7.2. Macromodel Development: Starting Assumptions.- 7.3. Degradation Macromodel for CMOS Inverters.- 7.4. Degradation Macromodel for nMOS Pass Gates.- 7.5. Application of the Macromodel to Inverter Chain Circuits.- 7.6. Application of the Macromodel to CMOS Logic Circuits.- References.- 8. Circuit Design for Reliability.- 8.1. Introduction.- 8.2. Device-Level Measures.- 8.3. Circuit-Level Measures.- 8.4. Rule-Based Diagnosis of Circuit Reliability.- References.