High Level Synthesis of ASICs under Timing and Synchronization Constraints
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Home > Science, Technology & Agriculture > Electronics and communications engineering > Electronics engineering > Electronics: circuits and components > High Level Synthesis of ASICs under Timing and Synchronization Constraints: (177 The Springer International Series in Engineering and Computer Science)
High Level Synthesis of ASICs under Timing and Synchronization Constraints: (177 The Springer International Series in Engineering and Computer Science)

High Level Synthesis of ASICs under Timing and Synchronization Constraints: (177 The Springer International Series in Engineering and Computer Science)


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About the Book

Computer-aided synthesis of digital circuits from behavioural level specifications offers an effective means to deal with the increasing complexity of digital hardware systems. This book addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioural level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. The text addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of an efficient data-path control-unit is the major contribution of this book. Three requirements are important in modelling ASIC designs: concurrency, external synchronization and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Table of Contents:
1 Introduction.- 2 System Overview.- 3 Behavioral Transformations.- 4 Sequencing Graph and Resource Model.- 5 Design Space Exploration.- 6 Relative Scheduling.- 7 Resource Conflict Resolution.- 8 Relative Control Generation.- 9 Relative Control Optimization.- 10 System Implementation.- 11 Experimental Results.- 12 Conclusions and Future Work.- References.


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Product Details
  • ISBN-13: 9780792392446
  • Publisher: Kluwer Academic Publishers
  • Publisher Imprint: Kluwer Academic Publishers
  • Height: 234 mm
  • No of Pages: 294
  • Returnable: Y
  • Width: 156 mm
  • ISBN-10: 0792392442
  • Publisher Date: 31 May 1992
  • Binding: Hardback
  • Language: English
  • Returnable: Y
  • Series Title: 177 The Springer International Series in Engineering and Computer Science


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High Level Synthesis of ASICs under Timing and Synchronization Constraints: (177 The Springer International Series in Engineering and Computer Science)
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High Level Synthesis of ASICs under Timing and Synchronization Constraints: (177 The Springer International Series in Engineering and Computer Science)
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