Delay Fault Testing for VLSI Circuits: (14 Frontiers in Electronic Testing)

With the ever-increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is further expected to grow with the late 20th-century design trend of moving towards deep submicron devices. After a long period of prevailing belief that high stuck-at fault coverage is sufficient to guarantee high quality of shipped products, the industry is now forced to rethink other types of testing. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed. Presenting a selection of existing delay testing research results, this volume combines introductory material with state-of-the-art techniques that address some of the problems in delay testing in the late 1990s. This text covers some basic topics such as fault modelling and test application schemes for detecting delay defects. It also presents summaries and conclusions of several recent case studies and experiments related to delay testing. A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. The book is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires a basic background in digital testing. It can also be used as supplementary material for a graduate-level course on VLSI testing.

Table of Contents:
1. Introduction.- 1.1 A Problem of Interest.- 1.2 Overview of the book.- 2. Test Application Schemes for Testing Delay Defects.- 2.1 Combinational Circuits.- 2.2 Sequential Circuits.- 2.3 Testing High Performance Circuits Using Slower Testers.- 2.4 Summary.- 3. Delay Fault Models.- 3.1 Transition Fault Model.- 3.2 Gate Delay Fault Model.- 3.3 Line Delay Fault Model.- 3.4 Path Delay Fault Model.- 3.5 Segment Delay Fault Model.- 3.6 Summary.- 4. Case Studies on Delay Testing.- 4.1 Summary.- 5. Path Delay Fault Classification.- 5.1 Sensitization Criteria.- 5.2 Path Delay Faults that do Not Need Testing.- 5.3 Multiple Path Delay Faults and Primitive Faults.- 5.4 Path Delay Fault Classification for Sequential Circuits.- 5.5 Summary.- 6. Delay Fault Simulation.- 6.1 Transition Fault Simulation.- 6.2 Gate delay fault simulation.- 6.3 Path Delay Fault Simulation.- 6.4 Segment Delay Fault Simulation.- 6.5 Summary.- 7. Test Generation for Path Delay Faults.- 7.1 Robust Tests.- 7.2 High Quality Non-Robust Tests.- 7.3 Validatable Non-Robust Tests.- 7.4 High Quality Functional Sensitizable Tests.- 7.5 Tests for Primitive Faults.- 7.6 Summary.- 8. Design for Delay Fault Testability.- 8.1 Improving The Path Delay Fault Testability by Reducing The Number of Faults.- 8.2 Improving The Path Delay Fault Testability by Increasing Robust Testability of Designs.- 8.3 Improving Path Delay Fault Testability by Increasing Primitive Delay Fault Testability.- 8.4 Summary.- 9. Synthesis for Delay Fault Testability.- 9.1 Synthesis for Robust Delay Fault Testability.- 9.2 Synthesis for Validatable Non-Robust Testable and Delay-Verifiable Circuits.- 9.3 Summary.- 10. Conclusions and Future Work.- References.