Cross-Talk Noise Immune VLSI Design Using Regular Layout Fabrics

This volume was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems such as cross-talk, electromigration, self-heat, etc. become important. Cross-talk is one of the major problems since it results in unpredictable design behaviour. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wire. Typical approaches to tackling the cross-talk problem attempt to fix the problem once it is created. This book introduces a framework for cross-talk-free IC design. The main foundation of the book is the use of a predetermined layout pattern on the IC, which we call a "layout fabric". The authors characterize this fabric and show how it yields cross-talk-immune designs. Two VLSI design flows are introduced which use the fabric concept. One flow is a minimally modified standard-cell based flow. The other flow uses a network of PLAs to implement the circuit. The authors also introduce "wire removal" techniques which improve circuit wire ability and thereby reduce circuit area. The new concepts presented here should be of interest to IC designers and researchers.

Table of Contents:
1. Introduction.- 1.1 Cross-talk in DSM IC Design.- 1.2 Book Overview.- 1.3 Book Outline.- 2. Validating Deep Sub-Micron Effects.- 2.1 Chapter Overview.- 2.2 Trends in DSM VLSI Interconnect.- 2.3 Predicting VLSI Process Technology Trends.- 2.4 Extracting On-chip Layout Parasitics.- 2.5 Validating Cross-talk Effects.- 2.6 Review of Existing Techniques.- 2.7 Chapter Summary.- 3. VLSI Layout Fabrics.- 3.1 Chapter Overview.- 3.2 Our Dense Wiring Fabric (DWF).- 3.3 Advantages.- 3.4 Disadvantages.- 3.5 Chapter Summary.- 4. Fabric1 - Fabric Cell Based Design.- 4.1 Chapter Overview.- 4.2 Design Flow 1.- 4.3 Design Flow 2.- 4.4 Chapter Summary.- 5. Fabric3 - Network of PLA Based Design.- 5.1 Chapter Overview.- 5.2 Programmable Logic Arrays.- 5.3 Networks of Programmable Logic Arrays.- 5.4 Synthesis Algorithms for the Network of PLAs Methodology.- 5.5 Design Flow 1.- 5.6 Design Flow 2.- 5.7 Discussion.- 5.8 Chapter Summary.- 6. Wire Removal in a Network of PLAS.- 6.1 Chapter Overview.- 6.2 Binary SPFDs.- 6.3 MV-SPFDs.- 6.4 Experimental Results.- 6.5 Chapter Summary.- 7. Conclusions and Future Directions.- 7.1 Conclusions.- 7.2 Future Work.- Appendices.- Standard Cells.