Hardware Description Languages: Concepts and Principles(IEEE Press Series on Microelectronic Systems)

"Hardware description languages (HDLs) hold the key to future processor designs, but until now no book has offered a clear analysis of the basic principles underlying HDLs. HARDWARE DESCRIPTION LANGUAGES is the first book to unlock the often hidden science of HDLs along with their origins and basic concepts. This indispensable guide explains HDLs and includes an insightful overview of the foremost HDLs of the past three decades, from "Computer Design Language" (CDL) to "Very High Speed Integrated Circuit" (VHSIC) to "VHSIC Hardware Description Language" (VHDL). To improve both your knowledge and digital designs of HDL fundamentals, this valuable book features these essential topics: * A critical review of VHDL and Verilog* Accurate modeling of hardware* Distributed simulation of behavior models* New semantics for transport delay. HARDWARE DESCRIPTION LANGUAGES is written for practicing electronic CAD engineers, researchers in simulation and verification of electronic CAD, graduate and doctoral students in computer design, and undergraduates specializing in electronic hardware design. Professors: To request an examination copy simply e--mail collegeadoption@ieee.org." Sponsored by: IEEE Solid--State Circuits Council/Society, IEEE Circuits and Systems Society.

Table of Contents:
Preface. Acknowledgments. List of Figures. List of Tables. The Origin of HDLs. Evolutionary Development of the Early HDLs. Fundamental Requirements of Behavior--level HDLs. The First Behavior--Level HDL--ADLIB--SABLE. Verilog HDL. Design of a Concurrent HDL in Ada from First Principles. VHDL. Case Studies: Developing Hardware Descriptions for Real--world Digital Systems. Simulation Algorithms for Concurrent Execution of HDLs on Loosely--coupled Parallel Processors. On the Concept of Transport Delay in HDLs. The Future of HDLs and Philosophical Reflection. Bibliography. Index. About the Author.

About the Author :
About the Author Sumit Ghosh is the associate chair for research and graduate programs in the Computer Science and Engineering Department at Arizona State University. Previously, he had been on the faculty at Brown University and has held research positions in private industry. Dr. Ghosh's research has pioneered work in areas such as preemptive semantics for inertial delays in hardware description languages; execution of VHDL models on distributed processors; behavior--level fault modeling; asynchronous distributed fault simulation; timing verification of asynchronous digital designs; deadlock--free distributed discrete event simulation algorithm (YADDES); dynamically reconfigurable computer architectures; and modeling and large--scale simulation of complex real--world systems. Dr. Ghosh's additional contributions include a fundamental framework for network security that has been incorporated into the National Security Agency's Network Rating Model; security on demand in ATM networks; a proposal to integrate the Department of Defense and public ATM network infrastructures; and the synthesis and validation of a comprehensive suite of security attack models for ATM networks. His research is the result of support from the IEEE Foundation, US AFOSR, US Army Research Office, DARPA, Bellcore, NYNEX, National Library of Medicine, NSF, Intel Corp., US Army Research Lab, US Ballistic Missile Defense Organization, National Security Agency, and US Air Force Labs in Rome, New York through Motorola.