Logic and Architecture Synthesis

The papers presented in this book cover the whole spectrum from high-level synthesis to technology mapping, including an overview of fifty years of logic synthesis and asking whether high-level synthesis is practical at all. The reader will undoubtedly be left with the impression that though the field of synthesis has made considerable progress in the last few years, there are still many problems to be dealt with.

Table of Contents:
Keynote Papers: Half a Century of Logic Synthesis (E.J. McCluskey). Is High Level Synthesis Practical? (R. Composano). High Level Synthesis. Symbolic Don't Cares and Equivalence in High-Level Synthesis (B. Lin, G.S. Whitcomb, A.R. Newton). Scheduling of Large Signal Flow Graphs Based on Metric Graph Clustering (F. Depuydt et al.). Profit-Loss-Gain Algorithm for Data-Path Synthesis (V. Techangam, A. Pitaksanonkul, C. Lursinap). A Novel Scheduling/Allocation Approach for Datapath Synthesis Based on Genetic Paradigms (N. Wehn, M. Held, M. Glesner). Port Assignment in Multiport Memories for Interconnection Minimization in Datapath Synthesis (T.C. Wilson et al.). Automatic Generation of Single Chip Multi Processor Systems (H.J. Kramer, W. Rosenstiel). A High-Level Synthesis Tool for Exploiting Pipelines in Special-Purpose Systems (B. Fjellborg). A High-Level Synthesis Algorithm Based on Area Oriented Design Transformations (W. Schenk). Logic and Architecture Synthesis. OASIS: A Silicon Compiler for Semi-Custom Design (G. Kedem, F. Brglez, K. Kozminski). High-Level Synthesis and Optimization Strategies in Hercules and Hebe (D. Ku, G. De Micheli). CASTOR: State Assignment in a Finite State Machine Synthesis System (G. Rietsche, M. Neher). Multi-Level Synthesis on Programmable Devices in the Asyl System (G. Saucier, P. Sicard, L. Bouchet). A Methodology for Performance Driven Data-Path Compilation (S. Note et al.). Automatic Synthesis of mu Programmed Controllers (L. Gerbaux, G. Saucier). Controller Synthesis. The Structure of Constant Rank State Machines (N.F. Benschop). State Reduction of Incompletely Specified Finite Sequential Machines (M.J. Avedillo, J.M. Quintana, J.L. Huertas). Determining the Optimal Cycle Time in Controller Synthesis (R. Zahir, W. Fichtner). A Formal Approach to Control-Unit Synthesis (M. Mahmood, F. Mavaddat, M.I. Elmasry). Low Level Synthesis. Efficient Computation of Exact and Simplified Observability Don't Care Sets for Multiple-Level Combinatorial Networks (M. Damiani, G. De Micheli). Lexicographical Factorization Minimizing the Critical Path and the Routing Factor of Multilevel Logic (P. Abouzeid, G. Saucier, F. Poirot). Corolla Partitions and Don't Cares (S. Dey, F. Brglez, G. Kedem). Combining Serial Decomposition with Topological Partitioning for Effective Multi-Level PLA Implementations (T. Luba et al.). Redesign and Automatic Error Correction of Combinatorial Circuits (M. Fujita, T. Kakuda, Y. Matsunaga). Technology Mapping. Automatic Layout of CMOS Cells (R. Jamier, J. Frehel). BAGDAD: An Oriented Layout Cell Synthesizer (J. Cloutier, J. Zahnd). Flexible and Optimizing ALU Synthesis (F. Buijs, P. Vogelgesang, T. Lengauer). Building Block Generation Considering the Inherent Hierarchy of Arithmetic Operations (A. Munzner). A Fast and Effective Technology Mapper on an Autodual Library of Standard Cells (K. Sakouti, G. Saucier). Case Studies.