Reconfigurable Processor Array
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Home > Computing and Information Technology > Computer science > Computer architecture and logic design > Parallel processing > Reconfigurable Processor Array: A Bit-sliced Parallel Computer(Research monographs in parallel & distributed computing)
Reconfigurable Processor Array: A Bit-sliced Parallel Computer(Research monographs in parallel & distributed computing)

Reconfigurable Processor Array: A Bit-sliced Parallel Computer(Research monographs in parallel & distributed computing)


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About the Book

A description of the development of a parallel computer of the single instruction-stream, multiple data-stream (SIMD) class. It is a type of SIMD computer known as a processor-array and the computer described here is known as the reconfigurable processor-array or RPA. For simple operations a large array of bit-serial processing elements is a better source of processing power than a small array of complex processors, and the RPA described here is enhanced with floating-point, multiplication and data cache facilities to improve the operation of such arrays. The RPA also has features which allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip deisgn, for possible VLSI realization, is described, and the appendix contains a high-level formal description of the processing element in a register-transfer language.

Table of Contents:
Part 1 Introduction to parallel computers: a brief history of parllel computers; types of parallel computer - the Flynn classification; why choose a processor-array? - SIMD versus MIMD; applications of processor-arrays - meteorology and oceanography, earth resources, medical, engineering design, signal processing, artificial intelligence; a case study of two SIMD networks - the distributed-array-processor (DAP), the connection machine. Part 2 Architecture of the reconfigurable processor-array: system description - overview of the RPA system; adaptive parallelism and reconfigurability - architecture of the bit-slice PE; data storage in the array; conditional operations; floating-point enhancements - mantissa alignment; a description of the RPA PE - instruction and ALU control field, external RAM port and host interface; RPA performance estimates. Part 3 Implementation of the RPA processor chip: choice of technology and design rules; design methodology - clocking scheme, layout of 16 PE chip, layout of 1 PE chip, gate matrix layout; design of the PE components; chip packaging. Part 4 Conclusions. Appendix: A register of transfer description of the PE and chip - the specification language and description of the PE and chip.


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Product Details
  • ISBN-13: 9780273087991
  • Publisher: Pearson Higher Education
  • Publisher Imprint: FT Prentice Hall
  • Height: 244 mm
  • Sub Title: A Bit-sliced Parallel Computer
  • Width: 169 mm
  • ISBN-10: 0273087991
  • Publisher Date: /01/1989
  • Binding: Paperback
  • Series Title: Research monographs in parallel & distributed computing
  • Weight: 312 gr


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Reconfigurable Processor Array: A Bit-sliced Parallel Computer(Research monographs in parallel & distributed computing)
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