Digital Electronics

Beginning with the fundamentals such as logic families, number systems, Boolean algebra and logic gates, and combinational circuits, Digital Electronics proceeds on to cover the applied aspects like sequential logic, ASM, programmable logic devices, converters and semiconductor memories. All the chapters in the book begin with outlining the contents of the chapters and include numerous solved examples and review questions to enhance the understanding of key concepts. Owing to its lucid style of presentation and a large number of numerical exercises and multiple choice questions at the end of the chapters, the book also serves as a self-preparatory material for students.

Table of Contents:
I. LOGIC FAMILIES; 1.1 INTRODUCTION; 1.2 LOGIC FAMILIES; 1.3 TRANSISTOR AS A SWITCH; 1.4 CHARACTERISTICS OF DIGITAL ICS; 1.4.1. SPEED OF OPERATION; 1.4.2. POWER DISSIPATION; 1.4.3. FIGURE OF MERIT; 1.4.4. FAN-OUT; 1.4.5. FAN-IN; 1.4.6. CURRENT AND VOLTAGE PARAMETERS; 1.4.7. NOISE IMMUNITY; 1.4.8. POWER SUPPLY REQUIREMENTS; 1.4.9. OPERATING TEMPERATURE; 1.5. RESISTOR - TRANSISTOR LOGIC (RTL); 1.6. DIRECT COUPLED TRANSISTOR LOGIC (DCTC); 1.7. DIODE - TRANSISTOR LOGIC (DTL); 1.8. MODIFIED DIODE - TRANSISTOR LOGIC; 1.9. TRANSISTOR - TRANSISTOR LOGIC (TTL); 1.9.1. TTL WITH PASSIVE PULL-UP; 1.9.2. TTL WITH TOTEM - POLE OUTPUT; 1.9.3. WIRED AND CONNECTION; 1.9.4. TTL WITH OPEN COLLECTOR OUTPUT; 1.9.5. UNCONNECTED INPUTS OF TTL; 1.9.6. TRI-STATETTL; 1.10. TTL PARAMETERS; 1.11. COMMONLY USED ICS OF STANDARD TTL; 1.12. IMPROVED TTL SERIES; 1.12.1. LOW POWER AND HIGH SPEED TTL; 1.12.2. SCHOTTKY TTL; 1.12.3. LOWER POWER SCHOTTKY TTL; 1.13. COMPARISON OF TTL FAMILIES; 1.14. EMITTER COUPLED LOGIC; 1.14.1. ECL CHARACTERISTICS; 1.15. INTEGRATED INJECTION LOGIC (I2L); 1.15.1. I2L INVERTER; 1.15.2. I2L NANDGATE; 1.15.3. I2L NOR GATE; 1.16. MOSFET LOGIC; 1.17. NMOS; 1.17.1. MNOS INVERTER; 1.17.2. NMOS NAND GATE; 1.17.3. NMOS NOR GATE; 1.17.4. FAN-OUT; 1.17.5. PROPAGATION DELAY TIME; 1.17.6. POWER DISSIPATION; 1.18. CMOS; 1.18.1. CMOS INVERTER; 1.18.2. CMOS NAND GATE; 1.18.3. CMOS NOR GATE; 1.18.4. CHARACTERISTICS OF CMOS; 1.18.5. BUFFERED AND UNBUFFERED GATES; 1.18.6. TRANSMISSION GATES; 1.18.7. OPEN DRAIN OUTPUTS; 1.18.8. HIGH IMPEDANCE OUTPUTS; 1.18.9. SPECIFICATIONS AND STANDARDS; 1.19. COMPARISON OF CMOS AND TTL FAMILIES; 1.20. INTERFACING CMOS AND TTL DEVICES; 1.20.1. TTL DRIVING CMOS; 1.20.2. CMOS DRIVING TTL; 1.21. INTERFACING OF ECL AND TTL DEVICES; 1.21.1. TTL DRIVING ECL; 1.21.2. ECL DRIVING TTL; 1.22. KEY TERMS & DEFINITIONS; 1.23. SUMMARY; 1.24. EXERCISE; 2. NUMBER SYSTEMS AND CODES; 2.1. INTRODUCTION; 2.2. NUMBER SYSTEMS; 2.3. INTERCONVERSION OF NUMBERS; 2.3.1. BINARY TO DECIMAL CONVERSION; 2.3.2. DECIMAL TO BINARY CONVERSION; 2.3.3. OCTAL TO DECIMAL CONVERSION; 2.3.4. DECIMAL TO OCTAL CONVERSION; 2.3.5. OCTAL TO BINARY CONVERSION; 2.3.6. BINARY TO OCTAL CONVERSION; 2.3.7. HEXADECIMAL TO DECIMAL CONVERSION; 2.3.8. DECIMAL TO HEXADECIMAL CONVERSION; 2.3.9. HEXADECIMAL TO BINARY CONVERSION; 2.3.10. BINARY TO HEXADECIMAL CONVERSION; 2.4. SIGNED BINARY NUMBER; 2.4.1. SIGN-MAGNITUDE REPRESENTATION; 2.4.2. 1'S COMPLEMENT REPRESENTATION; 2.4.3. 2'S COMPLEMENT REPRESENTATION; 2.5. FLOATING POINT REPRESENTATION OF NUMBER; 2.6. BINARY ARITHMETIC; 2.6.1. BINARY ADDITION; 2.6.2. BINARY SUBSTRACTION; 2.6.3. BINARY MULTIPLICATION; 2.6.4. BINARY DIVISION; 2.7. COMPLEMENT BINARY ARITHMETIC; 2.7.1. ONE'S (1'S) COMPLIMENT ARITHMETIC; 2.7.2. TWO'S (2'S) COMPLIMENT ARITHMETIC; 2.8. ARITHMETIC OVERFLOW; 2.9. CODES; 2.9.1. CLASSIFICATION OF CODES; 2.9.2. BINARY CODED DECIMAL CODE (BCD CODE); 2.9.2.1. BCD ARITHMETIC; 2.9.3. 2-4-2-1 CODE; 2.9.4. FOUR-BIT BCD CODES; 2.9.5. FIVE BIT BCD CODES; 2.9.6. BIQUINARY CODE; 2.9.7. EXCESS-3 CODE; 2.9.8. GRAY CODE; 2.9.8.1. BINARY TO GRAY CODE CONVERSION; 2.9.8.2. GRAY TO BINARY CODE CONVERSION; 2.9.9. SEVEN SEGMENT CODE; 2.9.10. ALPHANUMERIC CODES; 2.9.10.1. ASCII CODE; 2.9.10.2. EBCDIC CODE; 2.9.11. ERROR DETECTING CODES; 2.9.11.1. PARITY CODES; 2.9.11.2. BLOCK PARITY CODES; 2.9.12. ERROR CORRECTING CODES; 2.9.12.1. LINEAR BLOCK CODE; 2.9.12.2. HAMMING CODE; 2.10. SOLVED EXAMPLES; 2.11. SUMMARY; 2.12. EXERCISES; 2.13. PROBLEMS; 2.14. OBJECTIVE TYPE QUESTIONS; 3:BOOLEAN ALGEBRA AND LOGIC GATES; 3.1. INTRODUCTION; 3.2. BOOLEAN ALGEBRA; 3.2.1. PRINCIPAL OF LOGIC CIRCUITS; 3.2.2. BOOLEAN CONSTANTS, VARIABLES AND FUNCTIONS; 3.2.3. BASIC LAWS OF BOOLEAN ALGEBRA; 3.2.4. BOOLEAN THEOREMS; 3.3. OVERVIEW OF LOGIC CIRCUIT; 3.4. DEMORGAN'S THEOREMS; 3.5. STANDARD REPRESENTATION FOR LOGICAL FUNCTIONS; 3.5.1. SUM OF PRODUCTS FROM; 3.5.2. PRODUCTS OF SUMS; 3.6. MINTERM AND MAXTERM; 3.7. SIMPLIFICATION OF BOOLEAN EXPRESSION; 3.7.1. ALGEBRAIC METHOD; 3.7.2. KARNAUGH MAP SIMPLIFICATION; 3.7.2.1. REPRESENTATION OF K-MAP; 3.7.2.2. REPRESENTATION OF TRUTH TABLE ON K-MAP; 3.7.2.3. REPRESENTATION OF SUM OF PRODUCTS OF K-MAP; 3.7.2.4. REPRESENTATION OF PRODUCT OF SUM ON K-MAP; 3.7.2.5 .GROUPING THE ADJACENT CELLS; 3.8. SIMPLIFICATION OF SUM OF PRODUCT EXPRESSION; 3.9. SIMPLIFICATION OF PRODUCT OF SUMS EXPRESSION; 3.10. DON'T CARE CONDITION; 3.11. FIVE AND SIX VARIABLE K-MAP; 3.12. QUINE MCCLUSKEY METHOD; 3.13 SUMMARY; 3.14.EXERCISE; 3.15 OBJECTIVE TYPE QUESTIONS; 4: COMBINATIONAL LOGIC CIRCUIT; 4.1. INTRODUCTION; 4.2. DESIGN PROCEDURE FOR COMBINATIONAL LOGIC CIRCUIT; 4.2.1; EXAMPLES OF COMBINATIONAL LOGIC CIRCUIT; 4.3. ADDERS; 4.3.1. HALF ADDER; 4.3.2. FULL ADDER; 4.3.3. N-BIT PARALLEL ADDER; 4.3.4. CARRY LOOK AHEAD ADDER; 4.3.5 IC 74LS83; 4.4. SUBTRACTOR; 4.4.1. HALF SUBTRACTOR; 4.4.2. FULL SUBTRACTOR; 4.4.3. N-BIT PARALLEL SUBTRACTOR; 4.4.4.FOUR BIT SUBTRACTOR USING ADDER; 4.4.4.1; 1'S COMPLEMENT SUBTRACTION; 4.4.4.2 1'S COMPLEMENT SUBTRACTION; 4.5. BCD ADDER; 4.6. BCD SUBTRACTOR; 4.6.1.9'S COMPLEMENT; 4.6.2.9'S COMPLEMENT SUBTRACTION; 4.6.3.10'SCOMPLEMENT; 4.6.4.10'S COMPLEMENT SUBTRACTION; 4.7. ARITHMETIC LOGIC UNIT (ALU); 4.8. COMPARATOR; 4.8.1 IC 7485 [4 BIT-COMPARATOR]; 4.9. PARITY GENERATOR; 4.9.1. EVEN PARITY GENERATOR; 4.9.2; ODD PARITY GENERATOR; 4.10. PARITY CHECKER; 4.10.1. EVEN PARITY CHECKER; 4.10.2 ODD PARITY CHECKER; 4.11 PARITY GENERATOR/CHECKER (IC74180); 4.12 MULTIPLEXER; 4.12.1. MULTIPLEXER TREE; 4.12.2. MULTIPLEXER APPLICATIONS; 4.13. DEMULTIPLEXER; 4.13.1. DEMULTIPLEXER TREE; 4.13.2. DEMULTIPLEXER APPLICATIONS; 4.14. CODE CONVERTERS; 4.14.1. BINARY TO BCD CONVERTER; 4.14.2. BCD TO BINARY CONVERTER; 4.14.3. BCD TO EXCESS - 3; 4.14.4. EXCESS - 3 TO BCD CODE CONVERTER; 4.14.5. BINARY TO GRAY CODE CONVERTER; 4.14.6. GRAY TO BINARY CODE CONVERTER; 4.14.7. BCD TO SEVEN-SEGMENT CODE CONVERTER; 4.14.8. BCD TO SEVEN-SEGMENT DISPLAY DECODER/DRIVER; 4.14.9. BASIC CONNECTION FOR DRIVING 7-SEGMENT DISPLAYS; 4.12.10..ICS OF SEVEN-SEGMENT DRIVER/DECODER; 4.15. PIN DIAGRAMS OF ICS; 4.16. KEY TERMS AND DEFINITIONS; 4.17. EXERCISE; 4.18. OBJECTIVE TYPE QUESTIONS; 5. SEQUENTIAL LOGIC; 5.1. INTRODUCTION; 5.2. ONE BIT MEMORY CELL; 5.2.1. ONE BIT MEMORY CELL USING TRANSISTORS; 5.2.2. ONE BIT MEMORY CELL USING NAND GATES; 5.2.3. ONE BIT MEMORY CELL USING NOR GATES; 5.3. CLOCKED S.R. FLIP-FLOP; 5.3.1. PRESET AND CLEAR INPUTS; 5.4. J-K FLIP-FLOP; 5.4.1. RACE-AROUND CONDITION; 5.4.2. MASTER-SLAVE J-K FLIP-FLOP; 5.5. D FLIP-FLOP; 5.6. T FLIP-FLOP; 5.7. EDGE TRIGGERED FLIP-FLOP; 5.8. CHARACTERSTICS OF FLIP-FLOP; 5.8.1. PROPAGATION DELAY (TP); 5.8.2. SET-UP TIME (TG); 5.8.3. HOLD-UP TIME (TN); 5.8.4. MAXIMUM CHECK FREQUENCY (FMAX); 5.8.5. ASYNCHRONOUS ACTIVE PULSE WIDTH; 5.8.6. CLOCK HIGH PULSE TIME AND LOW PULSE TIME; 5.9. FLIP-FLOP CONVERSION; 5.9.1. S-R. FLIP-FLOP TO T FLIP-FLOP; 5.9.2. S-R. FLIP-FLOP TO D FLIP-FLOP; 5.9.3. S-R. FLIP-FLOP TO J.K. FLIP-FLOP; 5.9.4. T FLIP-FLOP TO D FLIP-FLOP; 5.9.5. D FLIP-FLOP TO T FLIP-FLOP; 5.9.6. J-K. FLIP-FLOP TO T FLIP-FLOP; 5.9.7.J-K. FLIP-FLOP TO D FLIP-FLOP; 5.10APPLICATION OF FLIP-FLOPS; 5.10.1. BOUNCE ELIMINATION SWITCH; 5.10.2. REGISTERS; 5.10.3COUNTERS; 5.10.4RANDOM ACCESS MEMORY; 5.11. SEQUENTIAL LOGIC DESIGN (INTRODUCTION); 5.12. REGISTERS AND SHIFT REGISTERS; 5.12.1SERIAL IN SERIAL OUT SHIFT REGISTER; 5.12.2. SERIAL IN PARALLEL OUT SHIFT REGISTER; 5.12.3PARALLEL IN SERIAL OUT SHIFT REGISTER; 5.12.4. PARALLEL IN PARALLEL OUT SHIFT REGISTER; 5.12.5.BI-DIRECTIONAL SHIFT REGISTER; 5.12.6. UNIVERSAL REGISTER; 5.13. APPLICATIONS OF SHIFT REGISTER; 5.13.1. SERIAL TO PARALLEL CONVERTER; 5.13.2. PARALLEL TO SERIAL CONVERTER; 5.13.3. RING COUNTER; 5.13.4. JOHNSON COUNTER AND TWISTED RING COUNTER; 5.13.5. SEQUENCE GENERATOR; 5.13.6. SEQUENCE DETECTOR; 5.14. COMMONLY USED ICS FOR SHIFT REGISTER; 5.15.RIPPLE COUNTER; 5.15.1. UP/DOWN ASYNCHRONOUS COUNTER; 5.15.2. MODULUS 'M' ASYNCHRONOUS COUNTER; 5.15.3. COMMONLY USED ICS FOR ASYNCHRONOUS COUNTER; 5.16. SYNCHRONOUS COUNTER; 5.17. FLIP-FLOP EXCITATION TABLE; 5.17.1. EXCITATION TABLE OF R-S FLIP-FLOP; 5.17.2. EXCITATION TABLE OF J-K FLIP-FLOP; 5.17.3. EXCITATION TABLE OF T FLIP-FLOP; 5.17.4. EXCITATION TABLE OF DT FLIP-FLOP; 5.18. SYNCHRONOUS COUNTER DESIGN; 5.19. UP/DOWN COUNTER; 5.19.1. COMMONLY USED ICS FOR SYNCHRONOUS COUNTER; 5.19.2; 74191; 5.19.3; 74192; 5.20. CLOCKED SEQUENTIAL CIRCUIT; 5.20.1; MOORE CIRCUIT; 5.20.2; MEALY CIRCUIT; 5.21 ANALYSIS OF CLOCKED SEQUENTIAL CIRCUIT; 5.21.1; STATE TABLE; 5.21.2; STATE DIAGRAM; 5.22 DESIGN OF CLOCKED SEQUENTIAL CIRCUIT; 5.22.1; STATE TABLE; 5.22.2; STATE DIAGRAM; 5.22.3; STATE REDUCTION; 5.22.4; STATE ASSIGNMENT; 5.23 LOCKOUT CONDITION; 5.24 SEQUENCE GENERATOR; 5.25 SEQUENCE DETECTOR; 5.26. SUMMARY; 5.27. EXERCISE; 5.28. OBJECTIVE TYPE QUESTIONS; 6. ASYNCHRONOUS SEQUENTIAL CIRCUITS; 6.1 INTRODUCTION; 6.2 DESIGN OF FUNDAMENTAL MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS; 6.2.1 REALIZATION USING D FLIP-FLOPS; 6.2.2 REALIZATION USING JK FLIP-FLOPS; 6.3 DESIGN OF PULSE MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS; 6.4 INCOMPLETELY SPECIFIED STATE MACHINES; 6.5 PROBLEMS IN ASYNCHRONOUS CIRCUITS; 6.5.1 CYCLES; 6.5.2 RACES; 6.5.3 HAZARDS; 6.6 DESIGN OF HAZARD FREE SWITCHING CIRCUITS; 6.7 SUMMARY; 6.8 EXERCISE; 6.9 OBJECTIVE TYPE QUESTIONS; 7. ALGORITHMIC STATE MACHINES; 7.1. INTRODUCTION; 7.2. ALGORITHMIC STATE MACHINES (ASM); 7.2.1. STATE BOX; 7.2.2. DECISION BOX; 7.2.3. CONDITIONAL BOX; 7.2.4. ASM BLOCK; 7.3. REALIZATION OF ASM CHARTS; 7.3.1. TRADITIONAL SYNTHESIS FROM AN ASM CHART; 7.3.2. MULTIPLEXER CONTROLLER METHOD; 7.4. SOLVED PROBLEMS ON ASM CHARTS; 7.5. REGISTER TRANSFER LANGUAGE; 7.6. RTL NOTATIONS; 7.6.1. REGISTER TRANSFER STATEMENTS; 7.6.1.1SHIFT OPERATION; 7.6.1.2. ROTATE OPERATION; 7.6.2. LOGICAL OPERATION STATEMENT; 7.6.2.1. INVERSION OPERATION; 7.6.2.2. ANDING OPERATION; 7.6.2.3. ORING OPERATION; 7.6.3. CONNECTION OPERATION STATEMENT; 7.6.4. BRANCH STATEMENTS; 7.6.4.1. UNCONDITIONAL BRANCH STATEMENT; 7.6.4.2CONDITIONAL BRANCH STATEMENT; 7.6.5. CONDITIONAL TRANSFER STATEMENT; 7.6.6. COUNT STATEMENT; 7.6.7. DECLARATION STATEMENT; 7.6.8. BUS CONNECTION STATEMENT; 7.7. DATA UNIT CONSTRUCTION FROM AN RTL DESCRIPTION; 7.8. VHDL; 7.8.1. ENTITY - ARCHITECTURE PAIR; 7.8.2. ENTITY DECLARATION; 7.8.3. ARCHITECTURE BODY; 7.8.4. STRUCTURAL MODELING; 7.8.4.1. DESCRIPTION OF FULL ADDER ARCHITECTURE; 7.8.4.2. DECLARATIVE PART; 7.8.4.3. STATEMENT PART; 7.8.5. DATA FLOW MODELING; 7.8.5.1. WHEN - ELSE STATEMENT; 7.8.5.2. WITH - SELECT STATEMENT; 7.8.6. BEHAVIORAL STYLE OF MODELING; 7.8.7. SEQUENTIAL STATEMENTS USED IN BEHAVIORAL MODELING; 7.8.8. MIXED STYLE OF MODELING; 7.8.9. CONFIGURATIONS; 7.8.9.1. DEFAULT CONFIGURATIONS; 7.8.9.2. COMPONENT CONFIGURATION; 7.8.10. IMPORTANT DATA OBJECTS IN VHDL; 7.8.10.1. SIGNAL; 7.8.10.2. VARIABLE; 7.8.10.3. CONSTANT; 7.8.11. IMPORTANT DATA TYPES; 7.8.12, VHDL OPERATORS; 7.8.13. VHDL EXAMPLES; 7.9. SUMMARY; 7.11. EXERCISE; 8. PROGRAMMABLE LOGIC DEVICES; 8.1. INTRODUCTION; 8.2. PROGRAMMABLE LOGIC ARRAY; 8.2.1 INTERNAL DIAGRAM OF PLA; 8.2.1.1, INPUT BUFFER; 8.2.1.2. AND MATRIX; 8.2.1.3. OR MATRIX; 8.2.1.3. INVERT/NON-INVERT MATRIX; 8.2.1.4. OUTPUT BUFFER; 8.2.2. COMBINATIONAL LOGIC DESIGN USING PLA; 8.2.3. SEQUENTIAL LOGIC DESIGN USING PLA; 8.3. PROGRAMMABLE ARRAY LOGIC; 8.3.1. INTERNAL DIAGRAM OF PAL; 8.3.2. REGISTERED OUTPUT PALS; 8.3.3. CONFIGURABLE PALS; 8.3.4. COMBINATIONAL LOGIC DESIGN USING PALS; 8.3.5. SEQUENTIAL LOGIC DESIGN USING PAL; 8.4. GENERIC ARRAY LOGIC DEVICES (GALS); 8.4.1. ARCHITECTURE OF GAL 16V8; 8.5. CLASSIFICATION OF PLDS; 8.6. COMPLEX PROGRAMMABLE LOGIC DEVICES; 8.6.1. XILINX XC 9500 CPLD FAMILY; 8.6.1.1. INTERNAL ARCHITECTURE; 8.6.1.2. FUNCTION - BLOCK ARCHITECTURE; 8.6.1.3. I/O BLOCK OF XC 9500; 8.6.1.4. SWITCH MATRIX; 8.7. FIELD PROGRAMMABLE GATE ARRAY; 8.7.1. XILINX FPGA ARCHITECTURE; 8.7.1.1. CONFIGURABLE LOGIC BLOCK; 8.7.1.2. COMBINATIONAL FUNCTION GENERATOR; 8.7.1.3. FLIP-FLOP; 8.7.1.4. PROGRAMMABLE MULTIPLEXERS; 8.7.1.5, INPUT-OUTPUT BLOCK (IOB); 8.7.1.6. SWITCHING MATRIX STRUCTURE; 8.7.2. XC 4000 SERIES FPGA; 8.7.2.1. CONFIGURABLE LOGIC BLOCK OF XC 400; 8.7.2.2. INPUT - OUTPUT MOCK OF XC 4000; 8.7.2.3. PROGRAMMABLE INTERCONNECTS; 8.8. APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASICS); 8.8.1. FULL CUSTOM ASICS; 8. 8. 2. SEMI-CUSTOM ASICS; 8.8.2.1. STANDARD CELL BASED ASICS; 8.8.2.2. GATE ARRAY BASED ASICS; 8.9. SOLVED EXAMPLES; 8.10. SUMMARY; 8.11. EXERCISES; 9. CONVERTERS; 9.1. INTRODUCTION; 9.2. BASIC PRINCIPLE OF D/A CONVERTER; 9.2.1. DIGITAL TO ANALOG (D/A) CONVERTER CIRCUITS; 9.2.2. DIGITAL TO ANALOG CONVERTER; 9.2.3. SPECIFICATIONS OF D/A CONVERTER; BASIC PRINCIPLE OF ANALOG TO DIGITAL CONVERTER; 9.3.1ANALOG TO DIGITAL CONVERTER CIRCUITS; 9.3.2. PARALLEL COMPARATOR ANALOG TO DIGITAL CONVERTER (FLASH CONVERTER); 9.3.3 SUCCESSIVE-APPROXIMATION A/D CONVERTER; 9.3.4. DUAL SLOPE A/D CONVERTER; 9.3.5. SPECIFICATIONS FOR ANALOG TO DIGITAL CONVERTER; 9.4. D/A AND A/D CONVERTER ICS; 9.5. ADC 0809 (8 BIT A/D CONVERTER); 9.6. ADC-7109 (12 BIT BINARY A/D CONVERTER); 9.7. DAC 0808 (8-BIT D/A CONVERTER); 9.8. SOLVED EXAMPLES; 9.9. SUMMARY; 9.10. EXERCISES; 10. SEMICONDUCTOR MEMORIES; 10.1. INTRODUCTION; 10.2. MEMORY ORGANIZATION; 10.3. FUNCTIONAL DIAGRAM OF MEMORY; 10.4. MEMORY OPERATIONS; 10.5. EXPANDING MEMORY SIZE; 10.5.1. EXPANDING WORD SIZE; 10.5.2. EXPANDING WORD CAPACITY; 10.5.3. EXPANDING OF WORD SIZE AND WORD CAPACITY; 10.6. CHARACTERISTICS OF MEMORY DEVICES; 10.7. CLASSIFICATION OF SEMICONDUCTING MEMORIES; 10.8. READ AND WRITE MEMORY; 10.8.1. STATIC RAM; 10.8.2. DYNAMIC RAM; 10.8.3. COMPARISON BETWEEN SRAM AND; 10.8.4. COMMONLY USED ICS FOR RAM; 10.9. READ ONLY MEMORY (ROM); 10.10. MASKED ROM; 10.10.1. PROGRAMMABLE READ ONLY MEMORY (PROM): 10.10.2. ERASABLE PROGRAMMABLE READ ONLY MEMORY (EPROM); 10.10.3. ELECTRICAL ERASABLE PROGRAMMABLE READ ONLY MEMORY (EEPROM); 10.10.4. NVRAM; 10.11. SOLVED EXAMPLES; 10.12. SUMMARY; 10.13. EXERCISES

About the Author :
Dr GK Kharate is currently Principal of Matoshri College of Engineering and Research Centre, Nashik. He is also a fellow member of Institution of Electronics and Telecommunication Engineers (IETE) and a life member of many other professional bodies of repute like Indian Society for Technical Education (ISTE), Institution of Engineers (India) and Computer Society of India. A PhD from University of Pune, Dr Kharate has more than 20 years of teaching experience. He has received a grant of rupees three lakhs from the University of Pune for his research proposal. He has also published a number of articles in national and international journals of repute and organized several conferences and workshops on his areas of study.