About the Book
The first comprehensive, in-depth guide to chip scale packaging, this reference gives you cutting-edge information on the most important new development in electronic packaging since surface mount technology (SMT). Featuring the latest design techniques, plus details on more than 40 different types of CSP, "Chip Scale Package" hands engineers and designers the complete, professional set of working tools that they need to solve technical and design issues; find the most efficient, cost-effective CSP solutions for their deployments; and, answer questions on interfacing, speed, robustness, and more; compare properties of wirebonds, flip chips, rigid and flex substrates, wafer-level redistribution, and other CSP products.This title helps you get the latest information on new offerings from Fujitsu, GE, Hitachi, IBM, Matushita, Motorola, National Semiconductor, NEC, Sharp, Sony, Toshiba, Amkor, TT, LG Semicon, Mitsubishi, Shell Case, Tessera, Samsung, and other major companies; and learn about CSP products under development. A revolution in electronics, CSP is taking the electronics industry by storm.
Page after page, this standard-setting guide gives you both essential technical details and an eye-opening overview of this fast-developing field. No matter how you use "Chip Scale Package", you'll see why it's the resource of choice for those who want to be at the top of the game.
Table of Contents:
Part I: Flip Chip and Wire Bond for CSP.
Solder-Bumped Flip Chip and Wire-Bonding Chip on CSP Substrate.
Part II: Customized Leadframe Based CSPs.
Fujitsu's Small Outline No-Lead/C-Lead Package (SON/SOC).
Fujitsu's Bump Chip Carrier (BCC).
Fujitsu's MicroBGA and Quad Flat Nonleaded Package (QFN).
Hitachi Cable's Lead-on-Chip Chip Scale Package (LOC-CSP).
Hitachi Cable's Micro Stud Array Package (MSA). LG
Semicon's Bottom-Leaded Plastic Package (BLP).
TI Japan's Memory Chip Scale Package with LOC (MCSP).
Part III: CSPs with Flexible Substrate.
3M's Enhanced Flex CSP.
General Electric's Chip-on-Flex Chip Scale Package (COF-CSP).
Hitachi's Chip Scale Package for Memory Devices.
IZM's flexPAC.
NEC's Fine-Pitch Ball Grid Array (FPBGA).
Nitto Denko's Molded Chip Size Package (MCSP).
Sharp's Chip Scale Package.
Tessera's Micro-Ball Grid Array.
TI Japan's Micro-Star BGA.
TI Japan's Memory Chip Scale Package with Flexible Substrate (MCSP).
Part IV: CSPs with Rigid Substrate.
Amkor/Anam's ChipArray Package.
EPS's Low-Cost Solder-Bumped Flip Chip NuCSP.
IBM's Ceramic Mini-Ball Grid Array
Package (Mini-BGA).
IBM's Flip Chip-Plastic Ball Grid Array Package (FC/PBGA).
Matsuhita's MN-PAC.
Motorola's SLICC and JACS-Pak.
National Semiconductor's Plastic Chip Carrier (PCC).
NEC's Three-Dimensional Memory Module (3DM) and CSP.
Sony's Transformed Grid Array Package (TGA).
Toshiba's Ceramic/Plastic Fine-Pitch BGA Package (C/P-FBGA).
Part V: Wafer-Level Redistribution CSPs.
ChipScale's Micro SMT Package (MSMT).
EPIC's Chip Scale Package.
Flip Chip Technologies' UltraCSP.
Fujitsu's Super CSP (SCSP).
Mitsubishi's Chip Scale Package (CSP).
National Semiconductor's SMD.
Sandia National Laboratories' Mini Ball Grid Array Package (mBGA).
ShellCase's Shell-PACK/Shell-BGA.
About the Author :
John H. Lau received his Ph.D. degree in Theoretical and Applied Mechanics from the University of Illinois (1977), a M.A.Sc. degree in Structural Engineering from the University of British Columbia (1973), a second M.S. degree in Engineering Physics from the University of Wisconsin (1974), and a third M.S. degree in Management Science from Fairleigh Dickinson University (1981). He also has a B.E. degree in Civil Engineering from National Taiwan University (1970). John is an interconnection technology scientist at Agilent Technologies, Inc. His current interests cover a broad range of electronic and optoelectronic packaging and manufacturing technology.
Prior to Agilent, he worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation, and Exxon Production and Research Company. With more than 30 years of R&D and manufacturing experience in the electronics, petroleum, nuclear, and defense industries, he has given over 200 workshops, authored and co-authored over 180 peer reviewed technical publications, and is the author and editor of 13 books: Solder Joint Reliability; Handbook of Tape Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects; Handbook of Fine Pitch Surface Mount Technology; Chip On Board Technologies for Multichip Modules; Ball Grid Array Technology; Flip Chip Technologies; Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Electronics Packaging: Design, Materials, Process, and Reliability; Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA, WLCSP, and PBGA Assemblies, and Microvias for Low Cost, High Density Interconnects.
John served as one of the associate editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and session chairman, and invited speaker of several IEEE, ASME, ASM, MRS, IMAPS, SEMI, and SMI International conferences. He received a few awards from ASME and IEEE for best papers and outstanding technical achievements, and is an ASME Fellow and an IEEE Fellow. He is listed in American Men and Women of Science and Who’s Who in America.
S.-W. Ricky Lee received his B.S., M.S. and Ph.D. degrees from National Taiwan University, VPI&SU and Purdue University, respectively. Currently Dr. Lee is Associate Professor of Mechanical Engineering at the Hong Kong University of Science & Technology (HKUST). He has contributed to numerous technical publications in various research areas and he is the co-author of two books on Chip Scale Packages and Microvias, respectively. Dr. Lee is very active in professional societies. He is a senior member of IEEE-CPMT, and a member of ASME and IMAPS. Also he is Chapter Chair of IEEE-CPMT Hong Kong Chapter. Dr. Lee's recent research activities are focused on flip chip technologies, wafer-level chip scale packaging, high density interconnects, and lead-free solders.
